MC74HCT259A
8-Bit Addressable Latch
1-of-8 Decoder with LSTTL
Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The HCT259A has four modes of operation as shown in the mode
selection table. In the addressable latch mode, the data on Data In is
written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous
states. In the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs. In the one−of−eight
decoding or demultiplexing mode, the addressed output follows the
state of Data In with all other outputs in the LOW state. In the Reset
mode all outputs are LOW and unaffected by the address and data
inputs. When operating the HCT259A as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
Features
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MARKING
DIAGRAMS
16
16
1
SOIC−16
D SUFFIX
CASE 751B
HCT259AG
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
HCT
259A
ALYWG
G
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
These are Pb−Free Devices
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RESET
ENABLE
DATA IN
Q7
Q6
Q5
Q4
MODE SELECTION TABLE
Enable
L
H
L
H
Reset
H
H
L
L
Mode
Addressable Latch
Memory
8−Line Demultiplexer
Reset
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
April, 2011
−
Rev. 3
1
Publication Order Number:
MC74HCT259A/D
MC74HCT259A
1
A0
2
A1
3
A2
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11
Q6
12
Q7
LATCH SELECTION TABLE
Address Inputs
NONINVERTING
OUTPUTS
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Latch Addressed
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
ADDRESS
INPUTS
DATA IN
13
15
RESET
14
ENABLE
PIN 16 = V
CC
PIN 8 = GND
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
V
ESD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Latchup Performance Above V
DD
and Below GND at
125°C (Note 3)
>2000
>200
±100
mA
SOIC Package
TSSOP Package
Value
−0.5
to +7.0
−0.5
to V
CC
+ 0.5
−0.5
to V
CC
+ 0.5
±20
±25
±50
500
450
−65
to + 150
Unit
V
V
V
mA
mA
mA
mW
°C
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
I
Latchup
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
1. Tested to EIA / JESD22−A114−A.
2. Tested to EIA / JESD22−A115−A.
3. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 2)
Min
4.5
0
−55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
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2
MC74HCT259A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input
Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
−
0.1 V
|I
out
|
v
20
mA
V
out
= 0.1 V or V
CC
−
0.1 V
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
|I
out
|
v
5.2 mA
|I
out
|
v
5.2 mA
V
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
−
55 to
25°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±
0.1
4
v
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±
1.0
40
v
125°C
2.0
2.0
0.8
0.8
4.4
5.4
3.70
0.1
0.1
0.40
±
1.0
160
mA
mA
V
Unit
V
V
V
DI
CC
≥
−55°C
5.5
2.9
25 to 125°C
2.4
mA
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3
MC74HCT259A
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5 to 5.5 V, C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PHL
t
TLH
,
t
THL
C
in
Parameter
Maximum Propagation Delay, Data to Output
(Figures 2 and 7)
Maximum Propagation Delay, Address Select to Output
(Figures 3 and 7)
Maximum Propagation Delay, Enable to Output
(Figures 4 and 7)
Maximum Propagation Delay, Reset to Output
(Figures 5 and 7)
Maximum Output Transition Time, Any Output
(Figures 2 and 7)
Maximum Input Capacitance
−55
to
25°C
32
32
32
22
15
10
v
85°C
32
40
40
26
19
10
v
125°C
42
45
45
32
22
10
Unit
ns
ns
ns
ns
ns
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)
30
pF
TIMING REQUIREMENTS
(V
CC
= 4.5 to 5.5 V, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
su
t
h
t
w
Parameter
Minimum Setup Time, Address or Data to Enable
(Figure 6)
Minimum Hold Time, Enable to Address or Data
(Figure 6)
Minimum Pulse Width, Reset or Enable
(Figure 4 or 5)
−55
to
25°C
15
1
15
v
85°C
19
1
19
v
125°C
22
1
22
Unit
ns
ns
ns
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MC74HCT259A
SWITCHING WAVEFORMS
3.0V
DATA IN
GND
3.0V
1.3 V
t
r
DATA IN
t
PLH
OUTPUT Q
90%
1.3 V
10%
t
TLH
50%
OUTPUT Q
t
THL
50%
90%
1.3 V
10%
t
PHL
t
PHL
t
PLH
t
f
3.0 V
GND
ADDRESS
SELECT
1.3 V
GND
GND
3.0V
Figure 2.
Figure 3.
3.0 V
DATA IN
t
w
ENABLE
1.3 V
t
PHL
OUTPUT Q
t
w
1.3 V
1.3 V
t
PLH
50%
GND
GND
V
CC
RESET
t
PHL
OUTPUT Q
50%
1.3 V
DATA IN
3.0V
GND
t
w
3.0V
GND
Figure 4.
Figure 5.
TEST POINT
DATA IN
OR
ADDRESS
SELECT
ENABLE
3.0V
1.3 V
t
h(H)
t
su
1.3 V
GND
*Includes all probe and jig capacitance
t
su
t
h(L)
GND
3.0V
DEVICE
UNDER
TEST
OUTPUT
C
L
*
Figure 6.
Figure 7. Test Circuit
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