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MC74HCT259ADG

Description
Latches 8-BIT ADDRESSABLE LATCH
Categorysemiconductor    logic   
File Size128KB,9 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC74HCT259ADG Overview

Latches 8-BIT ADDRESSABLE LATCH

MC74HCT259ADG Parametric

Parameter NameAttribute value
Product CategoryLatches
ManufacturerON Semiconductor
RoHSDetails
Logic TypeAddressable Latch
PolarityNon-Inverting
Propagation Delay Time45 ns
Supply Voltage - Max7 V
Supply Voltage - Min- 500 mV
Minimum Operating Temperature- 55 C
Maximum Operating Temperature+ 125 C
Package / CaseSOIC-16
PackagingTube
Mounting StyleSMD/SMT
Operating Supply Current50 mA
Factory Pack Quantity48
Unit Weight0.023492 oz
MC74HCT259A
8-Bit Addressable Latch
1-of-8 Decoder with LSTTL
Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The HCT259A has four modes of operation as shown in the mode
selection table. In the addressable latch mode, the data on Data In is
written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous
states. In the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs. In the one−of−eight
decoding or demultiplexing mode, the addressed output follows the
state of Data In with all other outputs in the LOW state. In the Reset
mode all outputs are LOW and unaffected by the address and data
inputs. When operating the HCT259A as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
Features
http://onsemi.com
MARKING
DIAGRAMS
16
16
1
SOIC−16
D SUFFIX
CASE 751B
HCT259AG
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
HCT
259A
ALYWG
G
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
These are Pb−Free Devices
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RESET
ENABLE
DATA IN
Q7
Q6
Q5
Q4
MODE SELECTION TABLE
Enable
L
H
L
H
Reset
H
H
L
L
Mode
Addressable Latch
Memory
8−Line Demultiplexer
Reset
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
April, 2011
Rev. 3
1
Publication Order Number:
MC74HCT259A/D

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