BLF9G38LS-90P
Power LDMOS transistor
Rev. 3 — 1 September 2015
Product data sheet
1. Product profile
1.1 General description
90 W LDMOS power transistor for base station applications at frequencies from
3400 MHz to 3600 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in the Doherty application demo circuit.
Test signal
IS-95
[1]
f
(MHz)
3400 to 3600
V
DS
(V)
28
P
L(AV)
(W)
15.1
G
p
(dB)
12.7
D
(%)
37.0
ACPR
(dBc)
37
[1]
Test signal: IS-95; pilot, paging, sync, 6 traffic channels with Walsh codes 8
13; PAR = 9.7 dB at 0.01 %
probability.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifier for LTE base stations and multi carrier applications in the
3400 MHz to 3600 MHz frequency range
BLF9G38LS-90P
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
Pinning
Description
drain1
drain2
gate1
gate2
source
[1]
Simplified outline
1
2
5
Graphic symbol
1
3
5
4
3
4
2
sym117
[1]
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name
BLF9G38LS-90P
-
Description
earless flanged ceramic package; 4 leads
Version
SOT1121B
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
[1]
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
5
65
[1]
Max
65
+13
+150
225
Unit
V
V
C
C
-
Continuous use at maximum temperature will affect the reliability, for details refer to the on-line MTF
calculator.
5. Thermal characteristics
Table 5.
Thermal characteristics
Conditions
T
case
= 80
C;
V
DS
= 28 V;
I
Dq
= 300 mA; V
GS(amp)peak
= 1.0 V
P
L
= 18 W (CW)
P
L
= 56 W (CW)
[1]
Measured in Doherty development circuit for thermal measurement
[1]
Symbol Parameter
R
th(j-case)
thermal resistance from junction to
case
Typ
Unit
0.37 K/W
0.22 K/W
BLF9G38LS-90P#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
2 of 15
BLF9G38LS-90P
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 0 V; I
D
= 0.513 mA
V
DS
= 10 V; I
D
= 51.3mA
V
DS
= 28 V; I
D
= 307.8 mA
V
GS
= 0 V; V
DS
= 32 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 51.3 mA
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 1.8 A
Min Typ
65
1.5
1.7
-
-
-
-
-
-
2.1
2.3
-
11
-
236
Max Unit
-
3.1
3.3
1.4
-
140
449
V
V
V
A
A
nA
S
m
0.45 -
Table 7.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f
1
= 3400 MHz; f
2
= 3500 MHz; f
3
= 3600 MHz; RF performance
at V
DS
= 28 V; I
Dq
= 600 mA; T
case
= 25
C; unless otherwise specified; in a class-AB production test
circuit at frequencies from 3400 MHz to 3600 MHz.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 20 W
P
L(AV)
= 20 W
P
L(AV)
= 20 W
P
L(AV)
= 20 W
Min
13.8
-
23
-
Typ
15.0
10
28
26
Max
-
6
-
21
Unit
dB
dB
%
dBc
7. Test information
7.1 Ruggedness in Doherty operation
The BLF9G38LS-90P is capable of withstanding a load mismatch corresponding to a
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 28 V;
I
Dq
= 300 mA; V
GS(amp)peak
= 0.7 V; P
L
= 56 W (CW); f = 3400 MHz; tested on the Doherty
development test circuit.
BLF9G38LS-90P#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
3 of 15
BLF9G38LS-90P
Power LDMOS transistor
7.2 Impedance information
Table 8.
Typical impedance of maximum power and drain efficiency
Measured load-pull data (half device); I
Dq
= 300 mA; V
DS
= 28 V; typical values unless otherwise
specified.
f
(MHz)
3400
3600
3800
3400
3600
3800
[1]
[2]
Z
S
[1]
()
7.0
j20.0
18.1
j29.7
47.2
j5.9
7.0
j20.0
18.1
j29.7
47.2
j5.9
Z
L
[1]
()
6.5
j14.1
7.9
j15.2
6.7
j16.7
9.3
j9.1
7.5
j10.3
7.0
j11.7
P
L
[2]
(W)
64
61
60
50
50
49
D
[2]
(%)
52.8
50.9
47.4
58.8
55.6
53.4
G
p
[2]
(dB)
12.2
12.5
11.7
14.1
14.1
14.1
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
Table 9.
Typical trade off impedance at 1 : 1 load
Measured load-pull data (half device); I
Dq
= 300 mA; V
DS
= 28 V; typical values unless otherwise
specified.
f
(MHz)
3400
3600
3800
[1]
[2]
Z
S
[1]
()
7.0
j20.0
18.1
j29.7
47.2
j5.9
Z
L
[1]
()
8.5
j12.3
7.3
j12.7
7.7
j13.9
P
L
[2]
(dBm)
60
59
56
D
[2]
(%)
57.9
54.7
52.3
G
p
[2]
(dB)
13.3
13.2
13.1
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 VBW in Doherty operation
The BLF9G38LS-90P shows 100 MHz (typical) video bandwidth in Doherty development
test circuit in 3500 MHz at V
DS
= 28 V; I
Dq
= 300 mA and V
GS(amp)peak
= 0.6 V.
BLF9G38LS-90P#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
4 of 15
BLF9G38LS-90P
Power LDMOS transistor
7.4 Test circuit
40 mm
40 mm
C13
C1
R1
P3
P4
C2
C3 R2
C9
C11
C7
C15
C17
P7
80 mm
P1
P2
P5
C5
C14
P6
C6
C12
C4
R3
C8
C10
C16
C18
aaa-018784
Printed-Circuit Board (PCB): Rogers RO4350B;
r
= 3.5; thickness = 0.508 mm;
thickness copper plating = 35
m.
See
Table 10
for a list of components.
Fig 2.
Component layout for Doherty development test circuit
Table 10. List of components
See
Figure 3
for component layout.
Component
C1, C3, C4, C6, C7,
C8, C10
C2, C5
C9
C11, C12, C13, C14
C15, C16
C17, C18
P1, P2, P3, P4, P5,
P6, P7
R1
R2, R3
Description
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
electrolytic capacitor
copper foil strip
SMD resistor
SMD resistor
Value
9.1 pF
0.9 pF
1.3 pF
1
F,
50 V
10
F,
50 V
2200
F,
63 V
-
50
5.1
needed for tuning
SMD 2512
SMD 0805
Remarks
ATC 600F
ATC 600F
ATC 600F
Murata
Murata
BLF9G38LS-90P#3
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 3 — 1 September 2015
5 of 15
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