MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
Rev. 6
03/2010
freescale.com
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
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MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 3)
Date
September,
2002
Revision
Level
N/A
Initial release
1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list.
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages.
Figure 2-1. Memory Map — Clarified illegal address and unimplemented
memory.
Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for
Port A Data Register (PTA) and Data Direction Register A (DDRA).
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard
interrupt and ADC conversion complete interrupt.
Chapter 13 System Integration Module (SIM) — Removed reference to break
status register as it is duplicated in break module.
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified
oscillator trim option ordering information and what to expect with untrimmed
device.
Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected.
December,
2002
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) —
Diagram updated for clarity.
0.1
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7,
DDRA7, and DDRA6.
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7.
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for
DDRA7 and DDRA6.
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1
Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion
of auto wakeup for clarity.
Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity.
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation.
Chapter 16 Electrical Specifications — Extensive changes made to electrical
specifications.
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case
outline drawing for DFN package.
Chapter 17 Ordering Information and Mechanical Specifications — Added
ordering information for DFN package.
January,
2003
0.2
4.2 Features — Corrected third bulleted item.
Description
Page
Number(s)
N/A
19
21
27
27
118
113
92
98
150
99
100
101
103
83
49
87
169
177
185
49
MC68HC908QY/QT Family Data Sheet, Rev. 6
4
Freescale Semiconductor
Revision History (Sheet 2 of 3)
Date
Revision
Level
Description
Reformatted to meet latest M68HC08 documentation standards
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator.
Table 1-2. Pin Functions — Added TCLK pin description.
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
add TCLK.
August,
2003
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
register (INTSCR) bits 3–0.
1.0
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values.
Figure 6-1. COP Block Diagram — Reworked for clarity
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
ACK, and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function.
15.3 Monitor Module (MON) — Updated with additional data.
Chapter 16 Electrical Specifications — Updated with additional data.
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented
areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available.
Also corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity
6.3.2 STOP Instruction — Added subsection
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
October,
2003
2.0
Table 13-2. Reset Recovery Timing — Replaced previous table with new
information.
Chapter 14 Timer Interface Module (TIM) — Updated with additional data.
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the
BRKAR register
15.3 Monitor Module (MON) — Clarified seventh bullet.
Table 17-1. MC Order Numbers — Corrected temperature and package
designators.
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
Oscillator Trim Value at $FFC0.
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
Page
Number(s)
N/A
20
21
22
23
26
47
51
59
77–79
131–139
147
169–173
27
59
60
111
112
131
143
147
175
January,
2004
32
3.0
38
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
5
Analogue and Mixed Signal
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