BLM7G1822S-40AB;
BLM7G1822S-40ABG
LDMOS 2-stage power MMIC
Rev. 2 — 1 September 2015
Product data sheet
1. Product profile
1.1 General description
The BLM7G1822S-40AB(G) is a dual section, asymmetric, 2-stage power MMIC using
Ampleon’s state of the art GEN7 LDMOS technology. This multiband device is perfectly
suited as small cell final in Doherty configuration, or as general purpose driver in the 1805
MHz to 2170 MHz frequency range. Available in gull wing or straight lead outline.
Table 1.
Performance
Typical RF performance at T
case
= 25
C; I
Dq1
= 20 mA; I
Dq2
= 76 mA for carrier section:
I
Dq1
= 40 mA and I
Dq2
= 120 mA for peaking section.
Test signal: 3GPP test model 1; single carrier W-CDMA; 64 DPCH; PAR = 9.9 dB at 0.01%
probability on CCDF; per section in a class-AB production circuit.
Test signal
single carrier W-CDMA
carrier section
peaking section
2167.5
2167.5
28
28
2
4
31.5
31.5
25.5
26.5
37
38
f
(MHz)
V
DS
(V)
P
L(AV)
(W)
G
p
(dB)
D
(%)
ACPR
5M
(dBc)
1.2 Features and benefits
Designed for broadband operation (frequency 1805 MHz to 2170 MHz)
High section-to-section isolation enabling multiple combinations
High Doherty efficiency thanks to 2 : 1 asymmetry
Integrated temperature compensated bias
Biasing of individual stages is externally accessible
Integrated ESD protection
Excellent thermal stability
High power gain
On-chip matching for ease of use
Compliant to Directive 2002/95/EC, regarding restriction of hazardous substances
(RoHS)
1.3 Applications
RF power MMIC for W-CDMA base stations in the 1805 MHz to 2170 MHz frequency
range. Possible circuit topologies are the following as also depicted in
Section 8.1:
Asymmetric final stage in Doherty configuration
Asymmetric driver for high power Doherty amplifier
BLM7G1822S-40AB(G)
LDMOS 2-stage power MMIC
2. Pinning information
2.1 Pinning
pin 1 index
V
DS(A1)
V
GS(A2)
V
GS(A1)
RF_IN_A
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RF_IN_B
V
GS(B1)
V
GS(B2)
V
DS(B1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
RF_OUT_A / V
DS(A2)
15
RF_OUT_B / V
DS(B2)
aaa-009322
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Fig 1.
Pin configuration
2.2 Pin description
Table 2.
Symbol
V
DS(A1)
V
GS(A2)
V
GS(A1)
RF_IN_A
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RF_IN_B
V
GS(B1)
V
GS(B2)
V
DS(B1)
BLM7G1822S-40AB_S-40ABG#2
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
drain-source voltage of carrier section, driver stage (A1)
gate-source voltage of carrier section, final stage (A2)
gate-source voltage of carrier section, driver stage (A1)
RF input carrier section (A)
not connected
not connected
not connected
not connected
not connected
not connected
RF input peaking section (B)
gate-source voltage of peaking section, driver stage (B1)
gate-source voltage of peaking section, final stage (B2)
drain-source voltage of peaking section, driver stage (B1)
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 September 2015
2 of 19
BLM7G1822S-40AB(G)
LDMOS 2-stage power MMIC
Table 2.
Symbol
Pin description
…continued
Pin
Description
RF output peaking section (B) / drain-source voltage of peaking
section, final stage (B2)
RF output carrier section (A) / drain-source voltage of carrier section,
final stage (A2)
RF_OUT_B/V
DS(B2)
15
RF_OUT_A/V
DS(A2)
16
GND
flange RF ground
3. Ordering information
Table 3.
Ordering information
Package
Name
BLM7G1822S-40AB
BLM7G1822S-40ABG
HSOP16F
HSOP16
Description
plastic, heatsink small outline package; 16 leads (flat)
plastic, heatsink small outline package; 16 leads
Version
SOT1211-2
SOT1212-2
Type number
4. Block diagram
V
DS(A1)
RF_IN_A
carrier
RF_OUT_A / V
DS(A2)
V
GS(A1)
V
GS(A2)
TEMPERATURE
COMPENSATED BIAS
V
GS(B1)
V
GS(B2)
TEMPERATURE
COMPENSATED BIAS
RF_IN_B
V
DS(B1)
peaking
RF_OUT_B / V
DS(B2)
aaa-016004
Fig 2.
Block diagram
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
Parameter
drain-source voltage
gate-source voltage
Conditions
Min
-
0.5
Max
65
+13
Unit
V
V
BLM7G1822S-40AB_S-40ABG#2
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 September 2015
3 of 19
BLM7G1822S-40AB(G)
LDMOS 2-stage power MMIC
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
T
stg
T
j
T
case
[1]
Parameter
storage temperature
junction temperature
case temperature
Conditions
[1]
Min
65
-
-
Max
+150
225
150
Unit
C
C
C
Continuous use at maximum temperature will affect the reliability. For details refer to the online MTF
calculator.
6. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
final stage; T
case
= 90
C;
P
L
= 1.78 W
driver stage; T
case
= 90
C;
P
L
= 1.78 W
Peaking section
R
th(j-c)
thermal resistance from junction to case
final stage; T
case
= 90
C;
P
L
= 1.26 W
driver stage; T
case
= 90
C;
P
L
= 1.26 W
[1]
When operated with a CW signal.
[1]
[1]
[1]
[1]
Value
3.8
12.4
2.4
7.6
Unit
K/W
K/W
K/W
K/W
Carrier section
7. Characteristics
Table 6.
DC characteristics
T
case
= 25
C; per section unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Carrier section
Final stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
V
GS
= 0 V; I
D
= 150.8
A
V
DS
= 28 V; I
D
= 76 mA
V
DS
= 28 V; I
D
= 76 mA
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.65 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
V
GS
= 0 V; I
D
= 30.16
A
V
DS
= 28 V; I
D
= 20 mA
V
DS
= 28 V; I
D
= 20 mA
I
Dq
/T
I
DSS
I
DSX
I
GSS
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.65 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
All information provided in this document is subject to legal disclaimers.
65
1.6
[1]
[1]
-
2.1
2.65
1
-
2.8
-
-
2.15
2.7
1
-
0.55
-
-
2.6
3.5
-
1.4
-
140
-
2.6
3.5
-
1.4
-
140
V
V
V
%
A
A
nA
V
V
V
%
A
A
nA
1.6
-
-
-
-
65
1.6
Driver stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
gate-source quiescent voltage
[2]
[2]
1.6
-
-
-
-
BLM7G1822S-40AB_S-40ABG#2
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 September 2015
4 of 19
BLM7G1822S-40AB(G)
LDMOS 2-stage power MMIC
Table 6.
DC characteristics
…continued
T
case
= 25
C; per section unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Peaking section
Final stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
V
GS
= 0 V; I
D
= 302
A
V
DS
= 28 V; I
D
= 120 mA
V
DS
= 28 V; I
D
= 120 mA
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.65 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
V
GS
= 0 V; I
D
= 58
A
V
DS
= 28 V; I
D
= 40 mA
V
DS
= 28 V; I
D
= 40 mA
I
Dq
/T
I
DSS
I
DSX
I
GSS
[1]
[2]
[3]
[4]
[4]
[4]
[3]
[3]
65
1.6
1.6
-
-
-
-
65
1.6
1.6
-
-
-
-
-
2.1
2.65
1
-
5.4
-
-
2.15
2.7
1
-
1.04
-
-
2.6
3.5
-
1.4
-
140
-
2.6
3.5
-
1.4
-
140
V
V
V
%
A
A
nA
V
V
V
%
A
A
nA
Driver stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
40 C
T
case
+85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.65 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
In production circuit with 1105.6
gate feed resistor.
In production circuit with 765
gate feed resistor.
In production circuit with 825.6
gate feed resistor.
In production circuit with 850
gate feed resistor.
Table 7.
RF Characteristics
Typical RF performance at T
case
= 25
C; V
DS
= 28 V; I
Dq1
= 20 mA (carrier section, driver stage); I
Dq2
= 76 mA (carrier
section, final stage); P
L(AV)
= 2 W (carrier section); I
Dq1
= 40 mA (peaking section, driver stage); I
Dq2
= 120 mA (peaking
section, final stage); P
L(AV)
= 4 W (peaking section) unless otherwise specified, measured in an Ampleon straight lead
production circuit.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Carrier section
Test signal: single carrier W-CDMA
[1]
G
p
D
RL
in
ACPR
5M
PAR
O
power gain
drain efficiency
input return loss
adjacent channel power ratio (5 MHz)
output peak-to-average ratio
f = 1807.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
f = 1807.5 MHz
f = 2167.5 MHz
-
30
-
21
-
-
-
-
6.4
31.8
31.5
18
25.5
15
39
37
8.4
7.7
-
33
-
-
10
-
33
-
-
dB
dB
%
%
dB
dBc
dBc
dB
dB
BLM7G1822S-40AB_S-40ABG#2
All information provided in this document is subject to legal disclaimers.
© Ampleon The Netherlands B.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 September 2015
5 of 19
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