NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX7DCEC
Rev. 5, 07/2017
MCIMX7DxDxxxxxD
MCIMX7DxExxxxxD
i.MX 7Dual Family of
Applications Processors
Datasheet
Package Information
Plastic Package
BGA 12 x 12 mm, 0.4 mm pitch
BGA 19 x 19 mm, 0.75 mm pitch
Ordering Information
See
Table 1 on page 3
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i.MX 7Dual introduction
1
The i.MX 7Dual family of processors represents NXP’s
latest achievement in high-performance processing for
low-power requirements with a high degree of functional
integration. These processors are targeted towards the
growing market of connected and portable devices.
The i.MX 7Dual family of processors features advanced
implementation of the ARM® Cortex®-A7 core, which
operates at speeds of up to 1 GHz and 1.2 GHz,
depending on the part number. The i.MX 7Dual family
provides up to 32-bit
DDR3/DDR3L/LPDDR2/LPDDR3-1066 memory
interface and a number of other interfaces for connecting
peripherals, such as WLAN, Bluetooth, GPS, displays,
and camera sensors.
2
3
4
5
6
7
i.MX 7Solo introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering information. . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1 Special signal considerations . . . . . . . . . . . . . . . . .15
3.2 Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Integrated LDO voltage regulator parameters . . . .34
4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . .36
4.4 On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . .36
4.5 I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . . .37
4.6 I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . . .41
4.7 Output buffer impedance parameters. . . . . . . . . . .45
4.8 System modules timing . . . . . . . . . . . . . . . . . . . . .47
4.9 General-purpose media interface (GPMI) timing . .67
4.10 External peripheral interface parameters . . . . . . . .75
4.11 12-Bit A/D converter (ADC) . . . . . . . . . . . . . . . . . 112
Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 113
5.1 Boot mode configuration pins . . . . . . . . . . . . . . . . 113
5.2 Boot device interface allocation . . . . . . . . . . . . . . 114
Package information and contact assignments . . . . . . . 116
6.1 12 x 12 mm package information . . . . . . . . . . . . . 116
6.2 19 x 19 mm package information . . . . . . . . . . . . .134
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2016–2017 NXP B.V.
i.MX 7Dual introduction
The i.MX 7Dual family of processors is specifically useful for applications such as:
• Audio
• Connected devices
• Access control panels
• Human-machine interfaces (HMI)
• Portable medical and health care
• IP phones
• Smart appliances
• Point of Sale
• eReaders
• Wearables
• Home energy management systems
The features of the i.MX 7Dual family of processors include the following:
• ARM Cortex-A7 plus ARM Cortex-M4—Heterogeneous Multicore Processing architecture
enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and
an RTOS like FreeRTOS™ on the Cortex-M4 core.
• Two ARM Cortex-A7 cores—The processor enhances the capabilities of portable, connected
applications by fulfilling the ever-increasing MIPS needs of operating systems and applications at
lowest power consumption levels per MHz.
• Multilevel memory system—The multilevel Cortex-A7 memory system is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, DDR3L, LPDDR2 and LPDDR3, NOR
Flash, NAND Flash (MLC and SLC), QSPI Flash, and managed NAND, including eMMC rev.
• Power efficiency—Power management implemented throughout the IC enables features and
peripherals to consume minimum power in both active and various low-power modes.
• Multimedia—The multimedia performance is enhanced by a multilevel cache system, NEON™
MPE (Media Processor Engine) coprocessor, a programmable smart DMA (SDMA) controller.
• Up to two Gigabit Ethernet with AVB—10/100/1000 Mbps Ethernet controllers supporting IEEE
Std 1588 time synchronization.
• Electronic Paper Display Controller (EPDC)—The processor integrates an EPD controller that
supports E Ink color and monochrome panels with up to 2048 x 1536 resolution at 106 Hz refresh,
4096 x 4096 resolution at 20 Hz refresh, and 5-bit grayscale (32-levels per color channel).
• Human-machine interface (HMI)—i.MX 7Dual processor provides up to two separate display
interfaces (parallel display and two-lane MIPI-DSI), CMOS sensor interface (two-lane MIPI-CSI
and parallel).
• Interface flexibility—i.MX 7Dual processor supports connections to a variety of interfaces: two
high-speed USB on-the-go modules with PHY, High-Speed Inter-Chip USB, multiple expansion
card ports (high-speed MMC/SDIO host and other), two Gigabit Ethernet controllers with support
for Ethernet AVB, PCIe-II, two 12-bit ADCs with a total of 8 single-ended inputs, two CAN ports,
and a variety of other popular interfaces (such as UART, I
2
C, and I
2
S).
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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NXP Semiconductors
i.MX 7Dual introduction
•
•
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 7Dual security
reference manual.
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different power domains. This significantly simplifies system power
management structure.
For a comprehensive list of the i.MX 7Dual features, see
Section 1.2, “Features.”
1.1
Ordering information
Table 1
provides examples of orderable sample part numbers covered by this data sheet.
Table 1. Orderable parts
Part Number
MCIMX7D7DVK10SD
Options
EPDC, CAN
2 x Gigabit Ethernet
4 tamper pins
1 x ADC
EPDC, CAN
2 x Gigabit Ethernet
10 tamper pins
2 x ADC
No EPDC, CAN
2 x Gigabit Ethernet
10 tamper pins
2 x ADC
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1 x ADC
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1 x ADC
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1x ADC
No EPDC, No CAN
2x Gigabit Ethernet
10 tamper pins
2x ADC
Cortex-A7 CPU
Qualification Tier
Speed Grade
1 GHz
Consumer
1
Temperature
(T
j
)
0 to +95°C
Package
12x12 mm
0.4 mm pitch
BGA
19x19 mm
0.75 mm pitch
BGA
19x19 mm
0.75 mm pitch
BGA
12x12 mm
0.4 mm pitch
BGA
MCIMX7D7DVM10SD
1 GHz
Consumer
1
0 to +95°C
MCIMX7D5EVM10SD
1 GHz
Industrial
2
-20 to 105°C
MCIMX7D3DVK10SD
1 GHz
Consumer
1
0 to +95°C
MCIMX7D3EVK10SD
1 GHz
Industrial
2
–20 to +105°C 12x12 mm
0.4 mm pitch
BGA
0 to 85°C
12x12 mm
0.4 mm pitch
BGA
19x19mm
0.75 mm pitch
BGA
MCIMX7D2DVK12SD
1.2 GHz
Consumer
MCIMX7D2DVM12SD
1.2 GHz
Consumer
0 to 85°C
1
2
Consumer qualification grade assumes 5-year lifetime with 50% duty cycle.
Industrial qualification grade assumes 10-year lifetime with 100% duty cycle.
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
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i.MX 7Dual introduction
Figure 1
describes the part number nomenclature so that the users can identify the characteristics of the
specific part number.
1
Restricted electrical specifications for parts with CPU maximum frequency of 1.2 GHz:
• Temperature range 0 to 85 degrees C (see Table 1)
• VDD_ARM requirements (see Table 9)
Figure 1. Part number nomenclature—i.MX 7Dual family of processors
1.2
Features
The i.MX 7Dual family of processors is based on ARM Cortex-A7 MPCore™ Platform, which has the
following features:
• Two ARM Cortex-A7 Cores (with TrustZone® technology)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— NEON MPE (media processing engine) coprocessor
The ARM Cortex-A7 Core complex shares:
• General interrupt controller (GIC) with 128 interrupt support
• Global timer
• Snoop control unit (SCU)
• 512 KB unified I/D L2 cache
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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NXP Semiconductors
i.MX 7Dual introduction
•
•
•
Two master AXI bus interfaces output of L2 cache
Frequency of the core (including NEON and L1 cache), as per
Table 9.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The ARM Cortex-M4 platform:
• Cortex-M4 CPU core
• MPU (memory protection unit)
• FPU (floating-point unit)
• 16 KByte instruction cache
• 16 KByte data cache
• 64 KByte TCM (tightly-coupled memory)
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (256 KB of total OCRAM)
— Secure/nonsecure RAM (32 KB)
• External memory interfaces: The i.MX 7Dual family of processors supports the latest,
high-volume, cost effective DRAM, NOR, and NAND Flash memory standards.
— Up to 32-bit LP-DDR2-1066, DDR3-1066, DDR3L-1066, and LPDDR3-1066
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 62 bits.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 7Dual processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
• Displays—Available interfaces.
— One parallel 24-bit display port
— One EPD port
— One MIPI DSI port
• Camera sensors:
— One parallel Camera port (up to 24 bit and up to 133 MHz peak)
— One MIPI-CSI port
• Expansion cards:
— Three MMC/SD/SDIO card ports all supporting the following. Moreover, the third port can
support HS400.
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
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