MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
◆
High logic densities and I/Os for increased logic integration
◆
◆
◆
◆
◆
— 128 to 512 macrocell densities
— 68 to 256 I/Os
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
Advanced E
2
CMOS process provides high performance, cost effective solutions
Select devices have been discontinued.
See Ordering Information section for product status.
Publication#
20446
Amendment/
0
Rev:
J
Issue Date:
April 2002
Table 1. MACH 5 Device Features
1
Feature
Supply Voltage (V)
Macrocells
Maximum User I/O Pins
t
PD
(ns)
t
SS
(ns)
t
COS
(ns)
f
CNT
(MHz)
Typical Static Power (mA)
IEEE 1149.1 Boundary Scan Compliant
PCI-Compliant
M5-128/1
M5LV-128
5
128
120
5.5
3.0
4.5
182
35
Yes
Yes
3.3
128
120
5.5
3.0
4.5
182
35
Yes
Yes
M5-192/1
5
192
120
5.5
3.0
4.5
182
45
Yes
Yes
M5-256/1
M5LV-256
5
256
160
5.5
3.0
4.5
182
55
Yes
Yes
3.3
256
160
5.5
3.0
4.5
182
55
Yes
Yes
M5-320
M5LV-320
5
320
192
6.5
3.0
5.0
167
70
Yes
Yes
3.3
320
160
6.5
3.0
5.0
167
70
Yes
Yes
M5-384
M5LV-384
5
384
160
6.5
3.0
5.0
167
75
Yes
Yes
3.3
384
160
6.5
3.0
5.0
167
75
Yes
Yes
M5-512
M5LV-512
5
512
256
6.5
3.0
5.0
167
100
Yes
Yes
3.3
512
256
6.5
3.0
5.0
167
100
Yes
Yes
Select devices have been discontinued.
See Ordering Information section for product status.
Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
GENERAL DESCRIPTION
The MACH
®
5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic
Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low
power, and supports additional features such as in-system programmability, Boundary Scan testability, and
advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx)
operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E
2
CMOS process technologies,
MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-
ns devices are compliant with the
PCI Local Bus Specification
.
2
MACH 5 Family
Table 2. MACH 5 Speed Grades
Speed Grade
1
Device
M5-128
2
M5-128/1
M5LV-128
M5-192/1
M5-256
2
-5
C
C
C
C
C
-6
-7
C
C, I
C,I
C, I
C
C, I
C, I
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-15
C, I
C, I
I
C, I
C, I
C, I
I
C, I
C, I
C, I
C, I
C, I
C, I
-20
I
I
I
Select devices have been discontinued.
See Ordering Information section for product status.
I
I
I
I
I
I
I
I
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
C
C
C
C
C
C
C, I
C, I
C, I
C, I
C, I
C, I
Note:
1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to
support full system logic integration. Extensive routing resources ensure pinout retention as well as high
utilization. It is ideal for PAL
®
block device integration and a wide range of other applications including high-
speed computing, low-power applications, communications, and embedded control. At each macrocell density
point, Lattice offers several I/O and package options to meet a wide range of design needs (Table 3).
Table 3. MACH 5 Package and I/O Options
1
M5-128/1
M5LV-128
Supply Voltage
100-pin TQFP
100-pin PQFP
144-pin TQFP
144-pin PQFP
160-pin PQFP
208-pin PQFP
240-pin PQFP
256-ball BGA
352-ball BGA
104
120
5
68
68
3.3
68, 74
68*
104
104*
120
104*
120
104*
120
160
M5-192/1
5
68
68*
M5-256/1
M5LV-256
5
68
68*
3.3
68*, 74
68
104
104*
120
160
120*
160
184*
192
120
160
184*
192*
120*
160
184*
192*
120
160
184*
192*
120*
160
184*
192*
256
120
160
184*
192*
256
M5-320
M5LV-320
5
3.3
M5-384
M5LV-384
5
3.3
M5-512
M5LV-512
5
3.3
Note:
1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.
Advanced power management options allow designers to incrementally reduce power while maintaining the
level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design,
MACH 5 Family
3
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The
block
interconnect
provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a
segment
. The second level of interconnect, the
segment interconnect
, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
Block:
16 MCs
CLK
4
Select devices have been discontinued.
See Ordering Information section for product status.
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆
I/O cells
◆
Product-term array and Logic Allocator
◆
Macrocells
◆
Register control generator
◆
Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback
.
If the I/O is used in another PAL block, the
interconnect feeder
assigns a
block interconnect
line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder
assigns block interconnect lines and local
feedback lines to the PAL block inputs.
4
MACH 5 Family
Block Interconnect
Segment:
4 Blocks
2
OE Generator
Control Generator
32
Logic Alocator
Macrocells
I/Os
Block
Feeder
Block Interconnect
Product-term
Array
32
Local Feedback
16
Select devices have been discontinued.
See Ordering Information section for product status.
32
Input Register
Path
2
Interconnect Feeder
20446G-002
Figure 2. PAL Block Structure
Product-Term Array and Logic Allocator
The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs
(plus their complements) and 64 product terms arranged in 16
clusters
. A cluster is a sum-of-products
function with either 3 of 4 product terms.
Logic allocators
assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or
four product terms, but a given cluster can only be steered to one macrocell (Table 4). If only three product
terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation
and/or polarity control.
The
wide logic allocator
is comprised of all 16 of the individual logic allocators and acts as an output switch
matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the
MACH 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass
through the logic array.
Table 4. Product Term Steering Options for PT Clusters and Macrocells
Macrocell
M
0
M
1
M
2
M
3
M
4
M
5
M
6
M
7
Available Clusters
C
0
, C
1
, C
2
, C
3
, C
4
C
0
, C
1
, C
2
, C
3
, C
4
, C
5
C
0
, C
1
, C
2
, C
3
, C
4
, C
5
, C
6
C
0
, C
1
, C
2
, C
3
, C
4
, C
5
, C
6
, C
7
C
0
, C
1
, C
2
, C
3
, C
4
, C
5
, C
6
, C
7
C
1
, C
2
, C
3
, C
4
, C
5
, C
6
, C
7
, C
8
C
2
, C
3
, C
4
, C
5
, C
6
, C
7
, C
8
, C
9
C
3
, C
4
, C
5
, C
6
, C
7
, C
8
, C
9
, C
10
Macrocell
M
8
M
9
M
10
M
11
M
12
M
13
M
14
M
15
Available Clusters
C
5
, C
6
, C
7
, C
8
, C
9
, C
10
, C
11
, C
12
C
6
, C
7
, C
8
, C
9
, C
10
, C
11
, C
12
, C
13
C
7
, C
8
, C
9
, C
10
, C
11
, C
12
, C
13
, C
14
C
8
, C
9
, C
10
, C
11
, C
12
, C
13
, C
14
, C
15
C
8
, C
9
, C
10
, C
11
, C
12
, C
13
, C
14
, C
15
C
9
, C
10
, C
11
, C
12
, C
13
, C
14
, C
15
C
10
, C
11
, C
12
, C
13
, C
14
, C
15
C
11
, C
12
, C
13
, C
14
, C
15
MACH 5 Family
5
京公网安备 11010802033920号
EEWORLD
