DS21554LB datasheet, PDF - EEWORLD Datasheet

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DS21554LB: DescriptionTelecom Interface ICs 3.3/5V E1 Transceiver; CategoryWireless rf/communication Telecom circuit; File Size922KB，124 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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Telecom Interface ICs 3.3/5V E1 Transceiver

DS21554LB Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	14 X 14 MM, LQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	1 week
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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DS21354/DS21554

3.3V/5V E1 Single-Chip Transceivers

www.maxim-ic.com

GENERAL DESCRIPTION

The DS21354/DS213554 single-chip transceivers

(SCTs) contain all the necessary functions to connect to

E1 lines. The devices are upward-compatible versions

of the DS2153 and DS2154 SCTs. The on-board

clock/data recovery circuitry coverts the AMI/HDB3 E1

waveforms to an NRZ serial stream. Both devices

automatically adjust to E1 22AWG (0.6mm) twisted-

pair cables from 0 to over 2km in length. They can

generate the necessary G.703 waveshapes for both 75W

coax and 120W twisted cables. The on-board jitter

attenuator (selectable to either 32 bits or 128 bits) can

be placed in either the transmit or receive data paths.

The framer locates the frame and multiframe

boundaries and monitors the data stream for alarms. It is

also used for extracting and inserting signaling data, Si,

and Sa-bit information. The on-board HDLC controller

can be used for Sa-bit links or DS0s. The devices

contain a set of internal registers that the user can

access to control the operation of the units. Quick

access through the parallel control port allows a single

controller to handle many E1 lines. The devices fully

meet all the latest E1 specifications, including ITU-T

G.703, G.704, G.706, G.823, G.732, and I.431, ETS

300 011, 300 233, and 300 166, as well as CTR12 and

CTR4.

FEATURES

Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceiver Functionality

On-Board Long- and Short-Haul Line Interface

for Clock/Data Recovery and Waveshaping

32-Bit or 128-Bit Crystal-Less Jitter Attenuator

Frames to FAS, CAS, CCS, and CRC4 Formats

Integral HDLC Controller with 64-Byte Buffers

Configurable for Sa Bits, DS0, or Sub-DS0

Operation

Dual Two-Frame Elastic Store Slip Buffers that

can Connect to Asynchronous Backplanes up to

8.192MHz

Interleaving PCM Bus Operation

8-Bit Parallel Control Port that can be used

Directly

Either

Multiplexed

Nonmultiplexed Buses (Intel or Motorola)

Extracts and Inserts CAS Signaling

Detects and Generates Remote and AIS Alarms

Programmable Output Clocks for Fractional E1,

H0, and H12 Applications

Fully Independent Transmit and Receive

Functionality

Full Access to Si and Sa Bits Aligned with

CRC-4 Multiframe

Four Separate Loopback Functions for Testing

Functions

Large Counters for Bipolar and Code Violations,

CRC4 Codeword Errors, FAS Word Errors, and

E Bits

IEEE 1149.1 JTAG-Boundary Scan Architecture

Pin Compatible with DS2154/52/352/552 SCTs

3.3V (DS21354) or 5V (DS21554) Supply; Low-

Power CMOS

100-pin LQFP package (14mm x 14mm)

PART

DS21354L

TEMP RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

100 LQFP

PIN CONFIGURATION

TOP VIEW

Dallas

Semiconductor

DS21354/DS21554

ORDERING INFORMATION

100

DS21354LN

LQFP

DS21554L

DS21554LN

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 124

REV: 021004

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

TABLE OF CONTENTS

1. INTRODUCTION.................................................................................................................. 6

1.1. F

UNCTIONAL

ESCRIPTION

..............................................................................................................................7

1.2. DOCUMENT REVISION HISTORY .............................................................................................................8

2. BLOCK DIAGRAM .............................................................................................................. 9

3. PIN DESCRIPTION............................................................................................................ 10

3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14

3.1.1.

Transmit-Side Pins..............................................................................................................................14

3.1.2.

Receive-Side Pins...............................................................................................................................17

3.1.3.

Parallel Control Port Pins ....................................................................................................................20

3.1.4.

JTAG Test Access Port Pins...............................................................................................................22

3.1.5.

Interleave Bus Operation Pins ............................................................................................................22

3.1.6.

Line Interface Pins ..............................................................................................................................23

3.1.7.

Supply Pins .........................................................................................................................................24

4. PARALLEL PORT ............................................................................................................. 25

4.1. REGISTER MAP ........................................................................................................................................25

5. CONTROL, ID, AND TEST REGISTERS .......................................................................... 30

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

POWER-UP SEQUENCE ..........................................................................................................................30

SYNCHRONIZATION AND RESYNCHRONIZATION...............................................................................32

FRAMER LOOPBACK ...............................................................................................................................36

AUTOMATIC ALARM GENERATION........................................................................................................38

REMOTE LOOPBACK ...............................................................................................................................40

LOCAL LOOPBACK...................................................................................................................................40

6. STATUS AND INFORMATION REGISTERS .................................................................... 43

6.1. CRC4 SYNC COUNTER............................................................................................................................45

7. ERROR COUNT REGISTERS........................................................................................... 50

7.1.

7.2.

7.3.

7.4.

BPV OR CODE VIOLATION COUNTER ...................................................................................................50

CRC4 ERROR COUNTER.........................................................................................................................51

E-BIT COUNTER .......................................................................................................................................51

FAS E

RROR

OUNTER

.................................................................................................................................52

8. DS0 MONITORING FUNCTION ........................................................................................ 53

9. SIGNALING OPERATION................................................................................................. 56

9.1. PROCESSOR-BASED SIGNALING ..........................................................................................................56

9.2. HARDWARE-BASED SIGNALING ............................................................................................................58

9.2.1.

Receive Side .......................................................................................................................................58

9.2.2.

Transmit Side ......................................................................................................................................59

10. PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 60

10.1. TRANSMIT-SIDE CODE GENERATION ................................................................................................60

10.1.1. Simple Idle Code Insertion and Per-Channel Loopback.....................................................................60

10.1.2. Per-Channel Code Insertion ...............................................................................................................61

10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62

11. CLOCK BLOCKING REGISTERS..................................................................................... 63

2 of 124

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

12. ELASTIC STORES OPERATION...................................................................................... 65

12.1. RECEIVE SIDE .......................................................................................................................................65

12.2. TRANSMIT SIDE.....................................................................................................................................65

13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................. 66

13.1. HARDWARE SCHEME ...........................................................................................................................66

13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME .........................................................66

13.3. INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME....................................................68

14. HDLC CONTROLLER FOR THE SA BITS OR DS0 ......................................................... 70

14.1. GENERAL OVERVIEW ...........................................................................................................................70

14.2. HDLC STATUS REGISTERS..................................................................................................................71

14.3. BASIC OPERATION DETAILS ...............................................................................................................72

14.3.1. Example: Receive an HDLC Message................................................................................................72

14.3.2. Example: Transmit an HDLC Message...............................................................................................72

14.4. HDLC REGISTER DESCRIPTION..........................................................................................................73

15. LINE INTERFACE FUNCTIONS........................................................................................ 80

15.1.

15.2.

15.3.

15.4.

15.5.

ECEIVE

LOCK AND

ATA

ECOVERY

.......................................................................................................81

RANSMIT

AVESHAPING AND

INE

RIVING

..............................................................................................81

ITTER

TTENUATOR

..................................................................................................................................82

ROTECTED

NTERFACES

...........................................................................................................................86

ECEIVE

ONITOR

ODE

..........................................................................................................................89

16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................... 90

16.1. I

NSTRUCTION

EGISTER

.............................................................................................................................95

16.2. T

EST

EGISTERS

.......................................................................................................................................96

17. INTERLEAVED PCM BUS OPERATION .......................................................................... 98

17.1. C

HANNEL

NTERLEAVE

...............................................................................................................................99

17.2. F

RAME

NTERLEAVE

...................................................................................................................................99

18. FUNCTIONAL TIMING DIAGRAMS................................................................................ 100

18.1. R

ECEIVE

.................................................................................................................................................100

18.2. T

RANSMIT

...............................................................................................................................................104

19. OPERATING PARAMETERS.......................................................................................... 111

20. AC TIMING PARAMETERS AND DIAGRAMS ............................................................... 112

20.1.

20.2.

20.3.

20.4.

ULTIPLEXED

AC C

HARACTERISTICS

................................................................................................112

ONMULTIPLEXED

AC C

HARACTERISTICS

..........................................................................................115

ECEIVE

-S

IDE

AC C

HARACTERISTICS

......................................................................................................117

RANSMIT

AC C

HARACTERISTICS

.............................................................................................................121

21. PACKAGE INFORMATION............................................................................................. 124

3 of 124

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

LIST OF FIGURES

Figure 2-1. DS21354/554 Block Diagram

............................................................................................................................. 9

Figure 15-1. Basic External Analog Connections

.............................................................................................................. 83

Figure 15-2. Optional Crystal Connection...........................................................................................................................

Figure 15-3. Jitter Tolerance.................................................................................................................................................

Figure 15-4. Jitter Attenuation

.............................................................................................................................................. 84

Figure 15-5. Transmit Waveform Template

........................................................................................................................ 85

Figure 15-6. Protected Interface Example for the DS21554

............................................................................................ 87

Figure 15-7. Protected Interface Example for the DS21354

............................................................................................ 88

Figure 15-8. Typical Monitor Port Application

.................................................................................................................... 89

Figure 16-1. JTAG Functional Block Diagram....................................................................................................................

Figure 16-2. TAP Controller State Diagram........................................................................................................................

Figure 17-1. IBO Basic Configuration Using Four SCTs

.................................................................................................. 99

Figure 18-1. Receive-Side Timing......................................................................................................................................

100

Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled).................................................................

100

Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)

.............................................. 101

Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)

.............................................. 101

Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode

................................................................................ 102

Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode.............................................................................

103

Figure 18-7. Transmit-Side Timing

.................................................................................................................................... 104

Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)................................................................

104

Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)

............................................. 105

Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)

........................................... 105

Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode

............................................................................. 106

Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode..........................................................................

107

Figure 18-13. G.802 Timing

................................................................................................................................................ 108

Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart

........................................................................ 109

Figure 18-15. DS21354/DS21554 Transmit Data Flow

.................................................................................................. 110

Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)...........................................................................................

113

Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1).................................................................................................

113

Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)

............................................................................................ 114

Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0)..........................................................................................

115

Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0)

.......................................................................................... 116

Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)..................................................................................

116

Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)

.................................................................................. 116

Figure 20-8. Receive-Side AC Timing

............................................................................................................................... 118

Figure 20-9. Receive System Side AC Timing.................................................................................................................

119

Figure 20-10. Receive Line Interface AC Timing.............................................................................................................

120

Figure 20-11. Transmit-Side AC Timing............................................................................................................................

122

Figure 20-12. Transmit System Side AC Timing..............................................................................................................

123

Figure 20-13. Transmit Line Interface Side AC Timing...................................................................................................

123

4 of 124

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

LIST OF TABLES

Table 3-1. Pin Description Sorted by Pin Number.............................................................................................................

Table 3-2. Pin Description by Symbol

................................................................................................................................. 12

Table 4-1. Register Map Sorted by Address

...................................................................................................................... 25

Table 5-1. Device ID Bit Map

................................................................................................................................................ 30

Table 5-2. SYNC/RESYNC Criteria

..................................................................................................................................... 32

Table 6-1. Alarm Criteria

....................................................................................................................................................... 46

Table 14-1. HDLC Controller Register List

......................................................................................................................... 70

Table 15-1. Line Build-Out Select in LICR for the DS21554

............................................................................................ 81

Table 15-2. Line Build-Out Select in LICR for the DS21354

............................................................................................ 82

Table 15-3. Transformer Specifications

.............................................................................................................................. 82

Table 15-4. Receive Monitor Mode Gain

............................................................................................................................ 89

Table 16-1. Instruction Codes for IEEE 1149.1 Architecture

........................................................................................... 95

Table 16-2. ID Code Structure..............................................................................................................................................

Table 16-3. Device ID Codes................................................................................................................................................

Table 16-4. Boundary Scan Control Bits.............................................................................................................................

Table 17-1. IBO Master Device Select

................................................................................................................................ 98

5 of 124

DS21554LB Related Products

	DS21554LB	DS21354L-	DS21354L	DS21554LN	DS21554L	DS21354LB	DS21354LN-	DS21354LN
Description	Telecom Interface ICs 3.3/5V E1 Transceiver	USB Interface IC Ultra Fast USB 2.19 Flash Media	Telecom Interface ICs 3.3/5V E1 Single Chip Transceiver	Telecom Interface ICs 3.3/5V E1 Transceiver	Telecom Interface ICs 3.3/5V E1 Transceiver	Telecom Interface ICs 3.3/5V E1 Single Chip Transceiver	Telecom Interface ICs 3.3/5V E1 Single Chip Transceiver	Telecom Interface ICs 3.3/5V E1 Single Chip Transceiver
Is it lead-free?	Contains lead	-	Contains lead	Contains lead	Contains lead	Contains lead	-	Contains lead
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	-	incompatible
Parts packaging code	QFP	-	QFP	QFP	QFP	QFP	-	QFP
package instruction	14 X 14 MM, LQFP-100	-	14 X 14 MM, LQFP-100	14 X 14 MM, LQFP-100	14 X 14 MM, LQFP-100	14 X 14 MM, LQFP-100	-	14 X 14 MM, LQFP-100
Contacts	100	-	100	100	100	100	-	100
Reach Compliance Code	not_compliant	-	not_compliant	not_compliant	not_compliant	not_compliant	-	not_compliant
ECCN code	EAR99	-	EAR99	-	EAR99	EAR99	-	EAR99
JESD-30 code	S-PQFP-G100	-	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	-	S-PQFP-G100
JESD-609 code	e0	-	e0	e0	e0	e0	-	e0
length	14 mm	-	14 mm	14 mm	14 mm	14 mm	-	14 mm
Humidity sensitivity level	3	-	3	3	3	3	-	3
Number of functions	1	-	1	1	1	1	-	1
Number of terminals	100	-	100	100	100	100	-	100
Maximum operating temperature	70 °C	-	70 °C	85 °C	70 °C	70 °C	-	85 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LFQFP	-	LFQFP	LFQFP	LFQFP	LFQFP	-	LFQFP
Package shape	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	-	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	245	-	240	240	245	245	-	240
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.6 mm	-	1.6 mm	1.6 mm	1.6 mm	1.6 mm	-	1.6 mm
Nominal supply voltage	5 V	-	3.3 V	5 V	5 V	3.3 V	-	3.3 V
surface mount	YES	-	YES	YES	YES	YES	-	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	-	CMOS
Telecom integrated circuit types	PCM TRANSCEIVER	-	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER	-	PCM TRANSCEIVER
Temperature level	COMMERCIAL	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	-	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING	GULL WING	GULL WING	GULL WING	-	GULL WING
Terminal pitch	0.5 mm	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm	-	0.5 mm
Terminal location	QUAD	-	QUAD	QUAD	QUAD	QUAD	-	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	20	20	NOT SPECIFIED	NOT SPECIFIED	-	20
width	14 mm	-	14 mm	14 mm	14 mm	14 mm	-	14 mm

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