19-5058; Rev 5/10
DS1643/DS1643P
Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
Clock Registers are Accessed Identically to the
Static RAM. These Registers Reside in the
Eight Top RAM Locations.
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
Access Times of 85ns and 100ns
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100
Power-Fail Write Protection Allows for ±10%
V
CC
Power Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time
DS1643 Only (DIP Module)
Standard JEDEC Byte-Wide 8K x 8 RAM
Pinout
UL Recognized
DS1643P Only (PowerCap Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-Fail Output
Pin-for-Pin Compatible with Other Densities of
DS164XP Timekeeping RAM
PIN CONFIGURATIONS
TOP VIEW
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
28
27
2
DS1643
26
3
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
14
16
15
V
CC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Encapsulated DIP
(700-mil Extended)
N.C.
N.C.
N.C.
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1643P
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
N.C.
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap Module Board
(Uses DS9034PCX PowerCap)
ORDERING INFORMATION
PART
DS1643-85+
DS1643-100+
DS1643P-85+
DS1643P-100+
VOLTAGE RANGE
(V)
5.0
5.0
5.0
5.0
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 EDIP (0.740)
28 EDIP (0.740)
34-PowerCap*
34-PowerCap*
TOP MARK
DS1643+85
DS1643+100
DS1643P+85
DS1643P+100
*
DS9034I-PCX+ and DS9034-PCX+ required (must be ordered separately).
+Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices.
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DS1643/DS1643P
PIN DESCRIPTION
PIN
PDIP
PowerCap
1, 2, 3,
1
31–34
2
30
3
25
4
24
5
23
6
22
7
21
8
20
9
19
10
18
21
28
23
29
24
27
25
26
11
16
12
15
13
14
15
13
16
12
17
11
18
10
19
9
20
8
22
7
26
—
27
6
28
5
—
14
—
4
17
NAME
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
OE
CE2
WE
V
CC
PFO
GND
X1, X2,
V
BAT
No Connection
FUNCTION
Address Inputs
Data Input/Output
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Chip-Enable 2 Input (Active High)
Active-Low Write-Enable Input
Power-Supply Input
Active-Low Power-Fail Output. This open-drain pin requires a
pullup resistor for proper operation.
Ground
Crystal Connection, Battery Connection
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DS1643/DS1643P
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) that are
both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to
any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to
avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1643 also contains its own power-fail circuitry, which deselects the device when the V
CC
supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap module. The 28-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1643P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double-buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to 0.
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DS1643/DS1643P
Figure 1. Block Diagram
DS1643/
DS1643P
Table 1. Truth Table
V
CC
5V
10%
CE
V
IH
X
V
IL
V
IL
V
IL
X
X
CE2
X
V
IL
V
IH
V
IH
V
IH
X
X
OE
WE
X
X
X
V
IL
V
IH
X
X
X
X
V
IL
V
IH
V
IH
X
X
MODE
Deselect
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High Z
High Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Standby
Active
Active
Active
CMOS Standby
Data Retention Mode
<4.5V >
V
BAT
<V
BAT
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e.,
CE
low,
OE
low, CE2 high, and address for seconds register remain valid and stable).
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DS1643/DS1643P
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within
1
minute per month at 25C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
1.53
minutes per month (35ppm) at 25C.
Table 2. Register Map—Bank1
ADDRESS
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
OSC
= STOP BIT
W = WRITE BIT
B
7
—
X
X
X
X
X
OSC
W
B
6
—
X
X
Ft
X
—
—
R
B
5
—
X
—
X
—
—
—
X
DATA
B
4
B
3
—
—
—
—
—
—
X
X
—
—
—
—
—
—
X
X
B
2
—
—
—
—
—
—
—
X
B
1
—
—
—
—
—
—
—
X
B
0
—
—
—
—
—
—
—
X
FUNCTION
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
A
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
Note:
All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever
WE
(write enable) is high and
CE
(chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
AA
after the last address input is stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times are not met, valid data will be
available at the latter of chip enable access (t
CEA
) or at output enable access time (t
OEA
). The state of the
data input/output pins (DQ) is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on
WE
will
then disable the outputs t
WEZ
after
WE
goes active.
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