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HCS86MS

Description
HC/UH SERIES, QUAD 2-INPUT XOR GATE, CDIP14
Categorysemiconductor    logic   
File Size172KB,8 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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HCS86MS Overview

HC/UH SERIES, QUAD 2-INPUT XOR GATE, CDIP14

HCS86MS
September 1995
Radiation Hardened
Quad 2-Input Exclusive OR Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x
10
12
RAD
(Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii
5µA at VOL, VOH
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
Description
The Intersil HCS86MS is a Radiation Hardened Quad 2-Input
Exclusive OR Gate. A high on any one input exclusively will
change the output to a High state.
The HCS86MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family with
either TTL or CMOS input compatibility.
The HCS86MS is supplied in a 14 lead Weld Seal Ceramic
flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package
(D suffix).
Functional Diagram
(1, 4, 9, 12)
An
Bn
(2, 5, 10, 13)
(3, 6, 8, 11)
Yn
Ordering Information
PART
NUMBER
HCS86DMSR
HCS86KMSR
HCS86D/
Sample
HCS86K/
Sample
HCS86HMSR
TEMPERATURE
RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
TRUTH TABLE
INPUTS
An
L
L
H
H
Bn
L
H
L
H
OUTPUTS
Yn
L
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
File Number
93
518773
3058.1

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