MITSUBISHI STORAGE CARD
ATA PC CARDS
8/16-bit Data Bus
Flash ATA PC Card
MF0064M-07BTxx
MF0128M-07BTxx
MF0256M-07BTxx
MF0512M-07BTxx
MF0640M-07BFxx
Connector Type
Two-piece 68-pin
DESCRIPTION
Mitsubishi
’
s Flash ATA cards provide large memory
capacities on a device approximately the size of a
credit card (85.6mm(L)
×
54mm(W)
×
3.3mm(T) or
5mm(T)). The cards use an 8/16 bit data bus.
Available in 64MB, 128MB, 256MB, 512MB and
640MB capacities, Mitsubishi
’
s Flash ATA cards
conform to the JEIDA/PCMCIA standard.
In default mode, the ATA card operates in PC Card
compliant sockets. It conforms to PCMCIA 2.1,JEIDA
4.2 and PC Card Standard.
When the OE# signal is asserted low level by the
Host system in power on cycle, the Mitsubishi
’
s Flash
ATA cards can be selected in a IDE ATA interface. It
uses the ATA command set so no software drivers
are required.
FEATURES
•
68pin PC Card Standard Type-I (up to 512MB) and
Type-II(640MB) PC Card
•
Single 5V or 3.3V Supply
•
Card density of up to 640MB maximum
•
Four PC Card ATA and IDE ATA modes
•
Nonvolatile, No Batteries Required
•
High reliability based on internal ECC function
•
Fast read/write performance(Target)
Read: 5MB/s(max.)
Write: 1.0MB/s(max.) (64MB)
2.0MB/s(max.) (128MB)
3.0MB/s(max.) (others)
100,000 program/erase cycles
•
APPLICATIONS
•
Computers
•
Digital Camera
•
Data Communication
•
Office Automation
•
Industrial
•
Consumer
PRODUCT LIST
Memory capacity
(Bytes)
64,094,208
128,057,344
257,163,264
515,579,904
640,475,136
Data Bus
width(bits)
Memory
256Mbit Flash x 2
256Mbit Flash x 4
256Mbit Flash x 8
256Mbit Flash x 16
256Mbit Flash x 20
Cylinder
978
977
981
999
1241
Head
4
8
16
16
16
Sector
32
32
32
63
63
Out line
MF0064M-07BTxx
MF0128M-07BTxx
MF0256M-07BTxx
MF0512M-07BTxx
MF0640M-07BFxx
Type I
8/16
TypeII
Jun.2000
. Rev. 1.0
MITSUBISHI
ELECTRIC
1/31
MITSUBISHI STORAGE CARD
MF0XXXX-07BTXX / -07BFXX series
ATA PC CARDS
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PC Card
Memory Mode
Signal
I/O
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
N.C
A9
A8
N.C
N.C
WE#
READY
Vcc
N.C
N.C
N.C
N.C
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
GND
-
I/O
I/O
I/O
I/O
I/O
I
I
I
-
I
I
-
-
I
O
-
-
-
-
-
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
-
PC Card I/O
Mode
Signal
I/O
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
N.C
A9
A8
N.C
N.C
WE#
IREQ#
Vcc
N.C
N.C
N.C
N.C
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
-
I/O
I/O
I/O
I/O
I/O
I
I
I
-
I
I
-
-
I
O
-
-
-
-
-
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
-
IDE ATA
Interface
Signal
I/O
GND
D3
D4
D5
D6
D7
CS0#
N.U
ATA SEL#
N.C
N.U
N.U
N.C
N.C
WE#
INTRQ
Vcc
N.C
N.C
N.C
N.C
N.U
N.U
N.U
N.U
N.U
A2
A1
A0
D0
D1
D2
IOCS16#
GND
-
I/O
I/O
I/O
I/O
I/O
I
-
I
-
-
-
-
-
I
O
-
-
-
-
-
-
-
-
-
-
I
I
I
I/O
I/O
I/O
O
-
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PC Card
Memory Mode
Signal
I/O
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
N.U
N.U
N.C
N.C
N.C
N.C
N.C
Vcc
N.C
N.C
N.C
N.C
CSEL
VS2#
RESET
WAIT#
N.U
REG#
BVD2
BVD1
D8
D9
D10
CD2#
GND
-
O
I/O
I/O
I/O
I/O
I/O
I
O
-
-
-
-
-
-
-
-
-
-
-
-
I
O
I
O
-
I
O
O
I/O
I/O
I/O
O
-
PC Card I/O
Mode
Signal
I/O
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
N.C
N.C
N.C
N.C
N.C
Vcc
N.C
N.C
N.C
N.C
CSEL
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
-
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
-
-
-
-
-
-
-
-
-
-
I
O
I
O
O
I
O
O
I/O
I/O
I/O
O
-
IDE ATA
Interface
Signal
I/O
GND
CD1#
D11
D12
D13
D14
D15
CS1#
VS1#
IORD#
IOWR#
N.C
N.C
N.C
N.C
N.C
Vcc
N.C
N.C
N.C
N.C
CSEL
VS2#
RESET#
IORDY
INPACK#
REG#
DASP#
PDIAG#
D8
D9
D10
CD2#
GND
-
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
-
-
-
-
-
-
-
-
-
-
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
O
-
N.C = Not connected internally. N.U = Not used.
Jun.2000
. Rev. 1.0
MITSUBISHI
ELECTRIC
2/31
MITSUBISHI STORAGE CARD
MF0XXXX-07BTXX / -07BFXX series
ATA PC CARDS
Signal Description
Signal Name
Address bus[A10-A0]
I/O
I
Pin No.
8, 11, 12, 22,
23, 24, 25, 26,
27, 28, 29
41, 40, 39, 38,
37, 66, 65, 64,
6, 5, 4, 3,
2 ,32,31, 30
7, 42
Description
Signals A10-A0 are address bus. A0 is invalid in
word mode. A10 is the MSB and A0 is the LSB.
Signals D15-D0 are data bus. D0 is the LSB of the
Even Byte of the Word. D8 is the LSB of the Odd
Byte of the Word.
CE1# and CE2# are low active card select signals.
Data bus[D15-D0]
I/O
Card Enable[CE1#, CE2#]
(PC Card Memory Mode)
Card Enable[CE1#, CE2#]
(PC Card I/O Mode)
Chip Select[CS0#, CS1#]
(IDE ATA Interface)
Output Enable[OE#]
(PC Card Memory Mode)
Output Enable[OE#]
(PC Card I/O Mode)
ATA SEL#
(IDE ATA Interface)
Write Enable[WE#]
(PC Card Memory Mode)
Write Enable[WE#]
(PC Card I/O Mode)
Write Enable[WE#]
(IDE ATA Interface)
I/O Read[IORD#]
(PC Card I/O Mode)
I/O Read[IORD#]
(IDE ATA Interface)
I/O Write[IOWR#]
(PC Card I/O Mode)
I/O Write[IOWR#]
(IDE ATA Interface)
Ready[READY]
(PC Card Memory Mode)
IREQ#
(PC Card I/O Mode)
INTRQ
(IDE ATA Interface)
Card Detection[CD1#, CD2#]
Write Protect[WP]
(PC Card Memory Mode)
IOIS16#
(PC Card I/O Mode)
IOCS16#
(IDE ATA Interface)
I
I
9
I
15
In IDE ATA Interface, CS0# is used to select the
Command Block Registers. CS1# is used to select
the Control Block Registers.
OE# is used to gate Attribute and Common
Memory Read data from the ATA Card.
OE# is used to gate Attribute Memory Read data
from the ATA Card.
To enable IDE ATA Interface, this input should be
grounded by the host.
WE# is used for strobing Attribute and Common
Memory Write data into the ATA Card.
WE# is used for strobing Attribute Memory Write
data into the ATA Card.
This input should be connected Vcc by the host.
IORD# is used to read data from the Card’s I/O
space.
I
44
I
45
IOWR# is used to write data to the Card’s I/O
space.
O
16
O
O
36, 67
33
READY signal is set high when the ATA Card is
ready to accept a new data transfer operation.
This signal of low level is indicates that the card is
requesting software service to host, and high level
indicates that the card is not requesting.
This signal is active high interrupt request to the
host.
CD1# and CD2# provided for proper detection of
PC Card insertion.
This signal is held low because this card does not
have a write protect switch.
This output signal is asserted when the I/O port
address is capable of 16-bit access.
Jun.2000
. Rev. 1.0
MITSUBISHI
ELECTRIC
3/31
MITSUBISHI STORAGE CARD
MF0XXXX-07BTXX / -07BFXX series
ATA PC CARDS
Signal Description(Continued)
Signal Name
Attribute Memory Select[REG#]
(PC Card Memory Mode)
Attribute Memory Select[REG#]
(PC Card I/O Mode)
Attribute Memory Select[REG#]
(IDE ATA Interface)
Battery Voltage Detect[BVD2]
(PC Card Memory Mode)
Audio Digital Waveform[SPKR#]
(PC Card I/O Mode)
DASP#
(IDE ATA Interface)
Card Reset[RESET]
(PC Card Memory Mode)
Card Reset[RESET]
(PC Card I/O Mode)
Card Reset[RESET#]
(IDE ATA Interface)
Wait[WAIT#]
(PC card Memory Mode)
Wait[WAIT#]
(PC card I/O Mode)
IORDY
(IDE ATA Interface)
Input Port Acknowledge[INPACK#]
(PC Card I/O Mode)
Input Port Acknowledge[INPACK#]
(IDE ATA Interface)
Battery Voltage Detect[BVD1]
(PC Card Memory Mode)
STSCHG#
(PC Card I/O Mode)
PDIAG#
(IDE ATA Interface)
Voltage Sense[VS1, VS2]
Cable Select[CSEL]
(PC card Memory Mode)
Cable Select[CSEL]
(PC card I/O Mode)
Cable Select[CSEL]
(IDE ATA Interface)
I/O
I
Pin No.
61
Description
When this signal is asserted, access is limited to
Attribute Memory with OE#/WE# and I/O Space
with
IORD#/IOWR#.
This input signal is not used for this mode and
should be connected to Vcc by the host.
This output is driven to a high-level.
SPKR# is kept negated because this Card does not
have digital audio output.
This signal is the DISK Active/Slave Present signal
in the Master/Slave handshake protocol.
By assertion of this signal, all registers of this Card
are cleared. This signal should be kept to High-Z by
the host for at least 1ms after Vcc applied.
This input pin is the active low hardware reset from
the host.
This signal is asserted to delay completion of the
memory or I/O access cycle.
O
62
I/O
I
58
O
59
O
60
This signal is asserted when the Card is selected
and can respond to an I/O Read cycle at the
address on the address bus.
This output is driven to a high-level.
This signal is asserted low to alert the host to
changes in the status of Configuration Status
Register in the Attribute Memory Space.
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
VS1 is grounded so that the Card CIS can be read
at 3.3V and VS2 is N.C.
This signal is not used for this mode.
O
63
I/O
O
-
-
I
43, 57
56
Vcc
GND
-
-
17, 51
1, 34, 35, 68
This signal is used to configure this Card as a
Master or a Slave. When this signal is grounded,
this Card is configured as a Master. When this
signal is Open, this Card is configure as a Slave.
5V or 3.3V power.
Ground.
Jun.2000
. Rev. 1.0
MITSUBISHI
ELECTRIC
4/31
MITSUBISHI STORAGE CARD
MF0XXXX-07BTXX / -07BFXX series
ATA PC CARDS
BLOCK DIAGRAM
Vcc
GND
Internal Vcc
Controller
A10-A0
CE1#/CS0#
CE2#/CS1#
OE#/ATA SEL#
WE#
IORD#
IOWR#
REG#
RESET/RESET#
D15-D0
READY/IREQ#/INTRQ
WP/IOIS16#/IOCS16#
INPACK#
BVD1/STSCHG#/PDIAG#
BVD2/SPKR#/DASP#
WAIT#/IORDY
CSEL
VS1
Open
POR#
RESET Circuit
RES#
CE#
OE#
WE#
CDE#
SC
I/O7-I/O0
R/B#
XIN
XOUT
Resonator
64Mbit AND
256Mbit AND
Flash Memory
Flash Memory
(x14)
(x20:640MB)
VS2
CD1#
CD2#
Jun.2000
. Rev. 1.0
MITSUBISHI
ELECTRIC
5/31
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