MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM72F10/D
8MB Synchronous Fast Static
RAM Module
The MCM72F10 (2MB) is configured as 1M x 72 bits. It is packaged in a
168–pin dual–in–line memory module DIMM. The module uses Motorola’s 3.3 V,
256K x 18 bit flow–through BurstRAMs.
Address (A), data inputs (DQ, DP), and all control signals except output enable
(G) are clock (K) controlled through positive–edge–triggered noninverting
registers.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W) allows writes to either individual bytes or to
both bytes.
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Single 3.3 V + 10%, – 5% Power Supply
Plug and Pin Compatibility with 1MB, 2MB, and 4MB
Multiple Clock Pins for Reduced Loading
All Inputs and Outputs are LVTTL Compatible
Byte Write Capability
Fast SRAM Access Times: 8/9/12 ns
High Quality Multi–Layer FR4 PWB With Separate Power and Ground
Planes
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Amp Connector, Part Number: 390064–4
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168–Pin DIMM Module
MCM72F10
168–LEAD DIMM
CASE TBD
TOP VIEW
1
11
40
41
84
REV 1
11/26/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM72F10
1
PIN DESCRIPTIONS
Pin Locations
59, 61, 62, 64, 65, 67, 68, 70,
71, 72, 143, 145, 146, 148,
149, 151, 152, 154, 155
156
15, 31, 44, 86, 92, 105, 121,
134
2, 3, 5, 6, 8, 9, 11, 12, 14, 17,
18, 20, 21, 23, 24, 26, 27, 32,
34, 35, 37, 38, 40, 41, 43, 46,
47, 49, 50, 52, 53, 55, 56, 87,
89, 90, 93, 95, 96, 98, 99,
101, 102, 104, 107, 108, 110,
111, 115, 116, 118, 119, 122,
124, 125, 127, 128, 130, 131,
133, 136, 137, 139, 140
83, 167
82, 166
Symbol
A0 – A18
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet
setup and hold times.
Synchronous Addresss Status Controller: Initiates read, write, or chip
deselect cycle.
Synchronous Parity Data Inputs/Outputs.
I/O
Synchronous Data Inputs/Outputs.
ADSP
DP0 – DP7
DQ0 – DQ63
Input
E0, E1
G0, G1
Input
Input
Synchronous Chip Enable: Active low to enable chip. Negated high —
blocks ADSP or deselects chip when ADSC is asserted.
Asynchronous Output Enable Input:
Low — enables output buffer.
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Synchronous Byte Write Inputs: x refers to the byte being written (byte a,
b).
Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.
Ground.
29, 74, 113, 158
76, 77, 79, 80, 160, 161, 163,
164
4, 16, 33, 45, 57, 69, 94, 106,
123, 135, 147, 165
1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,
88, 91, 97, 100, 103, 109,
112, 114, 117, 120, 126, 129,
132, 138, 141, 144, 150, 153,
157, 159, 162, 168
58, 142
K0 – K3
W0 – W7
VDD
VSS
Input
Input
Supply
Supply
NC
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, 3, and 4)
Next Cycle
Deselect
Begin Read
Read
Read
Begin Write
Write
Address Used
None
External Address
Current
Current
External
Current
E
1
0
X
X
0
X
ADSP
0
0
1
1
0
1
G
X
0
1
0
X
X
DQx
High–Z
DQ
High–Z
DQ
High–Z
High–Z
WRITE
X
Read
Read
Read
Write
Write
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. Write is defined as any Wx low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
MCM72F10
4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Power Supply Voltage
Voltage Relative to VSS
(See Note 2)
Input Voltage Three State I/O
(See Note 2)
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Storage Temperature
Symbol
VDD
Vin, Vout
VIT
Iout
PD
Tbias
Tstg
Value
– 0.5 to + 4.6
– 0.5 to VDD + 0.5
VSS – 0.5 to VDD + 0.5
±
20
4.6
– 10 to + 85
– 55 to + 125
Unit
V
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated volt-
ages to this high–impedance circuit.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing can not be controlled and
is not allowed.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS — PBGA
Rating
Junction to Ambient (@ 200 lfm)
Junction to Board (Bottom)
Junction to Case (Top)
Single Layer Board
Four Layer Board
Symbol
R
θJA
R
θJB
R
θJC
Max
41
19
11
19
Unit
°C/W
°C/W
°C/W
Notes
1, 2
3
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
MOTOROLA FAST SRAM
MCM72F10
5
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