MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69Q618/D
Advance Information
MCM69Q618
64K x 18 Bit Synchronous
Separate I/O Fast SRAM
The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized
as 64K words of 18 bits. It features separate data input and data output buffers and
incorporates input and output registers on board with high speed SRAM.
The MCM69Q618 allows the user to perform transparent write and data pass
through. Two data bus ports are provided – a data input (D) and a data output (Q) port.
The synchronous design allows for precise cycle control with the use of an external
single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write en-
able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the
rising edge of clock (K).
Any given cycle operates on only one address. However, for any cycle, reads and
writes can be intermixed. Thus, one can perform a read, a write, or a combination read/
write during any one cycle. For a combination read/write, the contents of the array are
read before the new data is written.
By using the pass–through function, the output port Q can be made to reflect either
the contents of the array or the data presented to the input port D. For read/write or a
read cycle with G low, the Q port will output the contents of the array. However, if PT
is asserted, the Q port will instead output the data presented at the D input port.
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Single 3.3 V
±
5% Power Supply
Fast Access Times: 6/8/10 ns Max
Sustained Throughput of 1.49 Gigabits/Second
Single Clock Operation
Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip
83 MHz Maximum Clock Cycle Time
Self Timed Write
Separate Data Input and Data Output Pins
Pass–Through Feature
Asynchronous Output Enable (G)
LVTTL Compatible I/O
No Dead Cycles Required for Reads after Writes or for Writes after Reads
100 Pin TQFP Package
Simultaneous Reads and Writes
— Routers
— Shared Memory
TQ PACKAGE
100 PIN TQFP
CASE 983A–01
Suggested Applications
— ATM
— Ethernet Switches
— Cell/Frame Buffers — SNA Switches
Product Family Configurations
Part
Number
Dual
Address
MCM69D536
MCM69D618
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909
n
n
Single
Address
Dual
I/O
Note 1
Note 1
n
n
n
n
n
n
Separate
I/O
Note 2
Note 2
n
n
n
n
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 5
11/24/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM69Q618
1
BLOCK DIAGRAM
K
A0 – A15
16
ADDRESS
REGISTER
64K x 18 ARRAY
W
WRITE
REGISTER
WRITE
DRIVER
SENSE
AMP
PT
PT
REGISTER
PASS–THROUGH
DATA INPUT
REGISTER
DATA OUTPUT
REGISTER
E1
E2
G
ENABLE
REGISTER 1
ENABLE
REGISTER 2
D0 – D17
Q0 – Q17
MCM69Q618
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
A6
NC
A7
NC
K
VDD
VSS
NC
G
E2
E1
NC
W
NC
PT
A8
NC
A9
NC
A15
VDD
VSS
D9
Q9
D10
Q10
VDD
VSS
D11
Q11
D12
Q12
VDD
VSS
Q13
D13
Q14
D14
VDD
VSS
Q15
D15
Q16
D16
VDD
VSS
Q17
D17
NC
A5
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
A4
NC
A3
NC
A2
NC
A1
NC
A0
VDD
A10
NC
A11
NC
A12
NC
A13
NC
A14
NC
VSS
VDD
D8
Q8
D7
Q7
VSS
VDD
D6
Q6
D5
Q5
VSS
VDD
Q4
D4
Q3
D3
VSS
VDD
Q2
D2
Q1
D1
VSS
VDD
Q0
D0
NC
MOTOROLA FAST SRAM
MCM69Q618
3
PIN DESCRIPTIONS
Pin Locations
30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,
81, 83, 85, 98, 100
3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58,
62, 64, 69, 71, 75, 77
90
91
92
Symbol
A0 – A15
D0 – D17
E1
E2
G
Type
Input
Input
Input
Input
Input
Description
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Data Input.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Chip Enable: Active high for depth expansion.
Asynchronous Output Enable Input:
Low — enables output buffers (Qx pins).
High — Qx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G.
Pass–through enable: Synchronous.
Synchronous Data Output.
Synchronous Write.
+ 3.3 V Power Supply.
Ground.
No Connection: There is no connection to the chip.
96
86
4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57,
59, 63, 65, 68, 70, 74, 76
88
1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95
2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94
29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51,
80, 82, 84, 87, 89, 93, 97, 99
K
PT
Q0 – Q17
W
VDD
VSS
NC
Input
Input
Output
Input
Supply
Supply
—
TRUTH TABLE
Input at tn Clock
Operation
O
i
Write and Pass–Through
Write/Read
Pass–Through
Read
Deselected
Deselected
E1
L
L
L
L
X
H
E2
H
H
H
H
L
X
W
L
L
H
H
X
X
PT
L
H
L
H
X
X
Data Input D
D written to A
D written to A
D data
Don’t Care
Don’t Care
Don’t Care
Result from tn + 1 Clock
Data Output Q
D data appears
Q out from A
D data appears
Q out from A
Q is high–Z
Q is high–Z
1
2
3
4
5
6
Notes
NOTES:
1. Write D to array and output D at Q.
2. Output contents of array to Q then write D to array.
3. Output D at Q. Do not write.
4. Output contents of array to Q. Do not write.
5. No operation.
6. No operation.
tn
K
tn + 1
ADDRESS & CONTROL
VALID
PIPELINED READ ACCESS
DATA INPUT D
VALID
PASS–THROUGH
DATA OUTPUT Q
VALID
MCM69Q618
4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VDD
Output Current
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
Symbol
VDD
Vin, Vout
Iout
PD
Tbias
TA
Tstg
Value
– 0.5 to + 4.6
– 0.5 to VDD + 0.5
±
20
TBD
– 10 to + 85
0 to + 70
– 55 to + 125
Unit
V
V
mA
W
°C
°C
°C
This is a synchronous device. All synchro-
nous inputs must meet specified setup and hold
times with stable logic levels for
ALL
rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS
(See Note 1)
Rating
Junction to Ambient (@ 200 lfm)
Junction to Board (Bottom)
Junction to Case (Top)
Single Layer Board
Four Layer Board
Symbol
R
θJA
R
θJB
R
θJC
TQFP
40
25
17
9
Unit
°C/W
°C/W
°C/W
Notes
2
3
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MOTOROLA FAST SRAM
MCM69Q618
5
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