MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69L736A/D
Advance Information
4M Late Write HSTL
The MCM69L736A/818A is a 4M synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L818A
(organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK a cycle after address and control
signals. Read data is available at the falling edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
•
•
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V +10%, – 5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Latch Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69L736A/818A–7.5 = 7.5 ns
MCM69L736A/818A–8.5 = 8.5 ns
MCM69L736A/818A–9.5 = 9.5 ns
MCM69L736A/818A–10.5 = 10.5 ns
•
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
MCM69L736A
MCM69L818A
ZP PACKAGE
PBGA
CASE 999–01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
4/3/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
1
FUNCTIONAL BLOCK DIAGRAM
DATA IN
REGISTER
DQ
DATA OUT
LATCH
SA
ADDRESS
REGISTERS
MEMORY
ARRAY
SW
SBx
CK
G
SW
REGISTERS
CONTROL
LOGIC
SS
SS
REGISTERS
PIN ASSIGNMENTS
TOP VIEW
MCM69L736A
1
A
B
C
D
E
DQc
F
G
DQc
H
J
K
L
DQd
M
VDDQ DQd
N
P
R
T
U
DQd
DQd
NC
NC
DQd
DQd
SA
NC
VSS
VSS
VSS
VDD
SA
TDI
SW
SA
SA
VDD
SA
TCK
VSS
VSS
VSS
VSS
SA
TDO
DQa VDDQ
DQa
DQa
SA
NC
DQa
DQa
NC
ZZ
N
P
R
T
NC
U
SA
SA
TDI
NC
TCK
SA
TDO
SA
ZZ
VDDQ TMS
NC VDDQ
DQd
SBd
CK
SBa
DQa
DQa
M
VDDQ DQb
DQb
NC
NC
NC
DQb
SA
VSS
VSS
VSS
VDD
SW
SA
SA
VDD
VSS
VSS
VSS
VSS
NC VDDQ
DQa
NC
SA
NC
DQa
NC
DQc
DQc
DQc
SBc
VSS
Vref
VSS
NC
NC
VDD
CK
SBb
VSS
Vref
VSS
DQb
DQb
DQb
DQb
H
J
K
L
DQc
VSS
VSS
SS
G
VSS
VSS
DQb
DQb
F
G
NC
DQb
DQb
NC
SBb
VSS
Vref
VSS
VSS
NC
NC
VDD
CK
CK
VSS
VSS
Vref
VSS
SBa
NC
DQa
DQa
NC
VDDQ DQc
DQb VDDQ
VDDQ
NC
NC
DQc
2
SA
NC
SA
DQc
3
SA
SA
SA
VSS
4
NC
NC
VDD
ZQ
5
SA
SA
SA
VSS
6
SA
NC
SA
DQb
7
VDDQ
NC
NC
DQb
A
B
C
D
E
NC
VDDQ
DQb
NC
VSS
VSS
SS
G
VSS
VSS
NC
DQa
DQa VDDQ
1
VDDQ
NC
NC
DQb
2
SA
NC
SA
NC
MCM69L818A
3
SA
SA
SA
VSS
4
NC
NC
VDD
ZQ
5
SA
SA
SA
VSS
6
SA
NC
SA
DQa
7
VDDQ
NC
NC
NC
VDDQ VDD
DQd
DQd
VDD VDDQ
DQa
DQa
VDDQ VDD
NC
DQb
DQb
NC
VDD VDDQ
NC
DQa
DQa
NC
VDDQ TMS
NC VDDQ
MCM69L736A•MCM69L818A
2
MOTOROLA FAST SRAM
MCM69L736A PIN DESCRIPTIONS
PBGA Pin Locations
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
4K
4L
4M
5L, 5G, 3G, 3L
(a), (b), (c), (d)
4E
4F
2U
3U
4U
5U
4D
7T
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
3J, 5J
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U
Symbol
SA
CK
CK
SW
SBx
Type
Input
Input
Input
Input
Input
Description
Synchronous Address Inputs: Registered on the rising clock edge.
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
Output Enable: Asynchronous pin, active low.
Test Mode Select (JTAG).
Test Data In (JTAG).
Test Clock (JTAG).
Test Data Out (JTAG).
Programmable Output Impedance: Programming pin.
Reserved for future use. Must be grounded.
Synchronous Data I/O.
SS
G
TMS
TDI
TCK
TDO
ZQ
ZZ
DQx
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Vref
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
Supply
—
Input Reference: Provides reference voltage for input buffers.
Core Power Supply.
Output Power Supply: Provides operating power for output buffers.
Ground.
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
3
MCM69L818A PIN DESCRIPTIONS
PBGA Pin Locations
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
4K
4L
4M
5L, 3G
(a), (b)
4E
2U
3U
4U
5U
4D
4F
7T
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
3J, 5J
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
Symbol
SA
CK
CK
SW
SBx
Type
Input
Input
Input
Input
Input
Description
Synchronous Address Inputs: Registered on the rising clock edge.
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
Test Mode Select (JTAG).
Test Data In (JTAG).
Test Clock (JTAG).
Test Data Out (JTAG).
Programmable Output Impedance: Programming pin.
Output Enable: Asynchronous pin, active low.
Reserved for future use. Must be grounded.
Synchronous Data I/O.
Input Reference: Provides reference voltage for input buffers.
Core Power Supply.
Output Power Supply: Provides operating power for output buffers.
Ground.
No Connection: There is no connection to the chip.
SS
TMS
TDI
TCK
TDO
ZQ
G
ZZ
DQx
Vref
VDD
VDDQ
VSS
NC
Input
Input
Input
Input
Output
Input
Input
Input
I/O
Supply
Supply
Supply
Supply
—
MCM69L736A•MCM69L818A
4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note 1)
Rating
Core Supply Voltage
Output Supply Voltage
Voltage On Any Pin
Input Current (per I/O)
Output Current (per I/O)
Power Dissipation (See Note 2)
Operating Temperature
Temperature Under Bias
Storage Temperature
Symbol
VDD
VDDQ
Vin
Iin
Iout
PD
TA
Tbias
Tstg
Value
– 0.5 to + 4.6
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
50
±
70
—
0 to + 70
–10 to + 85
– 55 to + 125
Unit
V
V
V
mA
mA
W
°C
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Junction to Ambient (Still Air)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board (Bottom)
Junction to Case (Top)
Single Layer Board
Four Layer Board
Symbol
R
θJA
R
θJA
R
θJA
R
θJB
R
θJC
Max
53
38
22
14
5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
3
4
Notes
1, 2
1, 2
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
5
京公网安备 11010802033920号
EEWORLD
