MCM69L818AZP8.5R datasheet, PDF

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MCM69L818AZP8.5R: Description4M Late Write HSTL; Categorystorage storage; File Size146KB，20 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM69L818AZP8.5R Overview

4M Late Write HSTL

MCM69L818AZP8.5R Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM69L736A/D

Advance Information

4M Late Write HSTL

The MCM69L736A/818A is a 4M synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69L818A

(organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

the RAM. At the rising edge of CK, all addresses, write enables, and synchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK a cycle after address and control

signals. Read data is available at the falling edge of CK.

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)

and output voltage (VDDQ) gives the system designer greater flexibility in

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

Single 3.3 V +10%, – 5% Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM69L736A/818A–7.5 = 7.5 ns

MCM69L736A/818A–8.5 = 8.5 ns

MCM69L736A/818A–9.5 = 9.5 ns

MCM69L736A/818A–10.5 = 10.5 ns

•

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

MCM69L736A

MCM69L818A

ZP PACKAGE

PBGA

CASE 999–01

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4/3/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69L736A•MCM69L818A

MCM69L818AZP8.5R Related Products

	MCM69L818AZP8.5R	MCM69L818AZP9.5	MCM69L818AZP7.5R	MCM69L818AZP9.5R	MCM69L818AZP8.5	MCM69L818AZP7.5	MCM69L736AZP9.5R	MCM69L736AZP9.5	MCM69L736A
Description	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL	4M Late Write HSTL

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