MCM67D709FN20 datasheet, PDF - EEWORLD Datasheet

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MCM67D709FN20: Description128K x 9 Bit Synchronous Dual I/O Fast Static RAM; Categorystorage storage; File Size93KB，12 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM67D709FN20 Overview

128K x 9 Bit Synchronous Dual I/O Fast Static RAM

MCM67D709FN20 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	PLASTIC, LCC-52
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	SELF-TIMED WRITE; DUAL I/O FOR SEPARATE PROCESSOR AND MEMORY BUSES
I/O type	COMMON
JESD-30 code	S-PQCC-J52
JESD-609 code	e0
length	19.1262 mm
memory density	1179648 bi
Memory IC Type	APPLICATION SPECIFIC SRAM
memory width	9
Number of functions	1
Number of ports	1
Number of terminals	52
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX9
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum slew rate	0.26 mA
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BICMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	19.1262 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM67D709/D

128K x 9 Bit Synchronous

Dual I/O Fast Static RAM

The MCM67D709 is a 1,179,648 bit synchronous static random access

memory organized as 131,072 words of 9 bits, fabricated using Motorola’s

high–performance silicon–gate BiCMOS technology. The device integrates a

128K x 9 SRAM core with advanced peripheral circuitry consisting of address

registers, two sets of input data registers and two sets of output latches. This

device has increased output drive capability supported by multiple power pins.

Asynchronous inputs include the processor output enable (POE) and the

system output enable (SOE).

The address inputs (A0 – A16) are synchronous and are registered on the

falling edge of clock (K). Write enable (W), processor input enable (PIE) and

system input enable (SIE) are registered on the rising edge of clock (K). Writes

to the RAM are self–timed.

All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP

have input data registers triggered by the rising edge of the clock. These pins also

have three–state output latches which are transparent during the high

level of the clock and latched during the low level of the clock.

This device has a special feature which allows data to be passed through the

RAM between the system and processor ports in either direction. This streaming

is accomplished by latching in data from one port and asynchronously output

enabling the other port. It is also possible to write to the RAM while streaming.

The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.

Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either

inputs (D) or outputs (Q) depending on the state of the control pins. In order to

dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs

(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.

PIE will need to track W for proper write/read operations.

This device is ideally suited for pipelined systems and systems with multiple

data buses and multi–processing systems, where a local processor has a bus

isolated from a common system bus.

•

Single 5 V

5% Power Supply

88110/88410 Compatibility: –16/60 MHz, –20/50 MHz

Self–Timed Write Cycles

Clock Controlled Output Latches

Address and Data Input Registers

Common Data Inputs and Data Outputs

Dual I/O for Separate Processor and Memory Buses

Separate Output Enable Controlled Three–State Outputs

3.3 V I/O Compatible

High Board Density 52 Lead PLCC Package

Can be used as Separate I/O x9 SRAM

MCM67D709

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENTS

SIE

PIE

SOE

POE

VCC

VSS

A16

A15

PDQ7

SDQ7

VSS

PDQ5

SDQ5

VCC

PDQ3

SDQ3

VSS

PDQ1

SDQ1

7 6 5 4 3 2 1 52 51 50 49 48 47

21 22 23 24 25 26 27 28 29 30 31 32 33

A14

A13

A12

A11

A10

VSS

VCC

PDQP

SDQP

VSS

PDQ6

SDQ6

VCC

PDQ4

SDQ4

PDQ2

SDQ2

VSS

PDQ0

SDQ0

PIN NAMES

A0 – A16 . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input

W . . . . . . . . . . . . . . . . . . . . . . . Write Enable

PIE . . . . . . . . . . . . . Processor Input Enable

SIE . . . . . . . . . . . . . . . System Input Enable

POE . . . . . . . . . . Processor Output Enable

SOE . . . . . . . . . . . . . System Output Enable

PDQ0 – PDQ7 . . . . . . . Processor Data I/O

PDQP . . . . . . . . . . . Processor Data Parity

SDQ0 – SDQ7 . . . . . . . . . System Data I/O

SDQP . . . . . . . . . . . . . System Data Parity

VCC . . . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must be

connected for proper operation of the

device.

REV2

5/95

Motorola, Inc. 1994

MOTOROLA FAST SRAM

MCM67D709

MCM67D709FN20 Related Products

	MCM67D709FN20	MCM67D709FN16	MCM67D709
Description	128K x 9 Bit Synchronous Dual I/O Fast Static RAM	128K x 9 Bit Synchronous Dual I/O Fast Static RAM	128K x 9 Bit Synchronous Dual I/O Fast Static RAM
Is it Rohs certified?	incompatible	incompatible	-
Maker	Motorola ( NXP )	Motorola ( NXP )	-
package instruction	PLASTIC, LCC-52	PLASTIC, LCC-52	-
Reach Compliance Code	unknow	unknow	-
ECCN code	3A991.B.2.A	3A991.B.2.A	-
Maximum access time	7.5 ns	6 ns	-
Other features	SELF-TIMED WRITE; DUAL I/O FOR SEPARATE PROCESSOR AND MEMORY BUSES	SELF-TIMED WRITE; DUAL I/O FOR SEPARATE PROCESSOR AND MEMORY BUSES	-
I/O type	COMMON	COMMON	-
JESD-30 code	S-PQCC-J52	S-PQCC-J52	-
JESD-609 code	e0	e0	-
length	19.1262 mm	19.1262 mm	-
memory density	1179648 bi	1179648 bi	-
Memory IC Type	APPLICATION SPECIFIC SRAM	APPLICATION SPECIFIC SRAM	-
memory width	9	9	-
Number of functions	1	1	-
Number of ports	1	1	-
Number of terminals	52	52	-
word count	131072 words	131072 words	-
character code	128000	128000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-
Maximum operating temperature	70 °C	70 °C	-
organize	128KX9	128KX9	-
Output characteristics	3-STATE	3-STATE	-
Exportable	YES	YES	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QCCJ	QCCJ	-
Encapsulate equivalent code	LDCC52,.8SQ	LDCC52,.8SQ	-
Package shape	SQUARE	SQUARE	-
Package form	CHIP CARRIER	CHIP CARRIER	-
Parallel/Serial	PARALLEL	PARALLEL	-
power supply	5 V	5 V	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	4.57 mm	4.57 mm	-
Maximum slew rate	0.26 mA	0.28 mA	-
Maximum supply voltage (Vsup)	5.25 V	5.25 V	-
Minimum supply voltage (Vsup)	4.75 V	4.75 V	-
Nominal supply voltage (Vsup)	5 V	5 V	-
surface mount	YES	YES	-
technology	BICMOS	BICMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	J BEND	J BEND	-
Terminal pitch	1.27 mm	1.27 mm	-
Terminal location	QUAD	QUAD	-
width	19.1262 mm	19.1262 mm	-

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