MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM67D709/D
128K x 9 Bit Synchronous
Dual I/O Fast Static RAM
The MCM67D709 is a 1,179,648 bit synchronous static random access
memory organized as 131,072 words of 9 bits, fabricated using Motorola’s
high–performance silicon–gate BiCMOS technology. The device integrates a
128K x 9 SRAM core with advanced peripheral circuitry consisting of address
registers, two sets of input data registers and two sets of output latches. This
device has increased output drive capability supported by multiple power pins.
Asynchronous inputs include the processor output enable (POE) and the
system output enable (SOE).
The address inputs (A0 – A16) are synchronous and are registered on the
falling edge of clock (K). Write enable (W), processor input enable (PIE) and
system input enable (SIE) are registered on the rising edge of clock (K). Writes
to the RAM are self–timed.
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
have input data registers triggered by the rising edge of the clock. These pins also
have three–state output latches which are transparent during the high
level of the clock and latched during the low level of the clock.
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.
Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either
inputs (D) or outputs (Q) depending on the state of the control pins. In order to
dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs
(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.
PIE will need to track W for proper write/read operations.
This device is ideally suited for pipelined systems and systems with multiple
data buses and multi–processing systems, where a local processor has a bus
isolated from a common system bus.
•
•
•
•
•
•
•
•
•
•
•
Single 5 V
±
5% Power Supply
88110/88410 Compatibility: –16/60 MHz, –20/50 MHz
Self–Timed Write Cycles
Clock Controlled Output Latches
Address and Data Input Registers
Common Data Inputs and Data Outputs
Dual I/O for Separate Processor and Memory Buses
Separate Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52 Lead PLCC Package
Can be used as Separate I/O x9 SRAM
MCM67D709
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
SIE
PIE
SOE
POE
WE
K
VCC
VSS
NC
A6
A4
A2
A0
A16
A15
PDQ7
SDQ7
VSS
PDQ5
SDQ5
VCC
PDQ3
SDQ3
VSS
PDQ1
SDQ1
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
A14
A13
A12
A11
A10
VSS
VCC
A9
A8
A7
A5
A3
A1
PDQP
SDQP
VSS
PDQ6
SDQ6
VCC
PDQ4
SDQ4
PDQ2
SDQ2
VSS
PDQ0
SDQ0
PIN NAMES
A0 – A16 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the
device.
REV2
5/95
©
Motorola, Inc. 1994
MOTOROLA FAST SRAM
MCM67D709
1
BLOCK DIAGRAM
PDQ0 – PDQ7, PDQP
POE
9
K
DATA
REGISTER
A0 – A16
128K x 9 ARRAY
REGISTER
WRITE
DRIVER
DATA
LATCH
CONTROL
DATA
REGISTER
SOE
SDQ0 – SDQ7,
SDQP Output
High–Z
Data Out
Data Out
High–Z
High–Z
High–Z
Data In
Stream Data
Data In
Stream Data
Data In
High–Z
Stream
High–Z
Data In
Data In
2, 4
2, 5
2, 5
2, 6
2, 6
2, 6
2, 6
4
2, 7
2, 7
2, 7
2, 7
9
SENSE
AMPLIFIER
DATA
LATCH
W
PIE
SIE
9
SDQ0 – SDQ7, SDQP
FUNCTIONAL TRUTH TABLE
(See Notes 1 and 2)
W
1
1
1
1
X
0
0
0
0
1
1
0
X
X
X
X
PIE
1
1
1
X
0
0
1
0
1
0
1
1
0
0
1
1
SIE
1
1
1
X
0
1
0
1
0
1
0
1
1
1
0
0
POE
0
1
0
1
X
1
1
1
0
1
0
X
0
0
0
1
SOE
1
0
0
1
X
1
1
0
1
0
1
X
0
1
0
0
Mode
Read
Read
Read
Read
N/A
Write
Write
Write
Write
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Memory Subsystem
Cycle
Processor Read
Copy Back
Dual Bus Read
NOP
NOP
Processor Write Hit
Allocate
Write Through
Allocate With Stream
Cache Inhibit Write
Cache Inhibit Read
NOP
Invalid
Invalid
Invalid
Invalid
PDQ0 – PDQ7,
PDQP Output
Data Out
High–Z
Data Out
High–Z
High–Z
Data In
High–Z
Data In
Stream Data
Data In
Stream Data
High–Z
Data In
Data In
Stream
High–Z
Notes
3
3
3
NOTES:
1. A ‘0’ represents an input voltage
≤
VIL and a ‘1’ represents an input voltage
≥
VIH. All inputs must satisfy the specified setup and hold times
for the falling or rising edge of K. Some entries in this truth table represent latched values. Other possible combinations of control inputs not
covered by this note or the table above are not supported and the RAMs behavior is not specified.
2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are
High–Z.
3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.
4. No RAM cycle is performed.
5. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and
PDQP or SDQ0 – SDQ7 and SPDQ), and written into the RAM.
6. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other
I/O port.
7. Data contention will occur.
MCM67D709
2
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Power Supply
Voltage Relative to VSS for Any Pin
Except VCC
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature
Symbol
VCC
Vin, Vout
Iout
PD
Tbias
TA
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
±
30
2.0
– 10 to + 85
0 to +70
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
(Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (POE, SOE = VIH)
AC Supply Current (All Inputs = VIL or VIH,VIL = 0.0 V and VIH
≥
3.0 V,
Iout = 0 mA, Cycle Time
≥
tKHKH min)
MCM67D709–16: tKHKH = 16 ns
MCM67D709–20: tKHKH = 20 ns
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
Symbol
VCC
VIH
VIL
Ilkg(I)
Ilkg(O)
ICCA
—
—
VOL
VOH
—
2.4
280
260
0.4
3.3
V
V
Min
4.75
2.2
– 0.5*
—
—
Max
5.25
VCC + 0.3**
0.8
±
1.0
±
1.0
Unit
V
V
V
µA
µA
mA
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance (All Pins Except I/Os)
Input/Output Capacitance (PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, SDQP)
Symbol
Cin
Cout
Typ
5
6
Max
6
7
Unit
pF
pF
MOTOROLA FAST SRAM
MCM67D709
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE
(See Note 1)
Processor Frequency
60 MHz
MCM67D709–16
Parameter
Read Cycle Time Clock High to Clock High
Clock Low Pulse Width
Clock High Pulse Width
Clock High to Output Valid
Clock (K) High to Output Low Z After Write
Output Hold from Clock High
Setup Times:
A
W
PIE
SIE
A
W
PIE
SIE
Symbol
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX1
tKHQX2
tAVKL
tWHKH
tPIEHKH
tSIEHKH
tKLAX
tKHWX
tKHPIEX
tKHSIEX
tPOEHQZ
tSOEHQZ
tPOEHQX
tSOEHQX
tPOELQX
tSOELQX
tPOELQV
tSOELQV
Min
16
5
7
—
0
2
2
2
2
2
2
2
2
2
0
2
0
—
Max
—
—
—
6
—
—
—
50 MHz
MCM67D709–20
Min
20
5
7
—
0
3
2
2
2
2
2
2
2
2
0
5
0
—
Max
—
—
—
7.5
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
3, 4
3
Notes
1, 2
Hold Times:
—
—
ns
Output Enable High to Q High–Z
Output Hold from Output Enable High
Output Enable Low to Q Active
Output Enable Low to Output Valid
6
—
—
5
8
—
—
6
ns
ns
ns
ns
4
4
4
NOTES:
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K, SOE, or POE.
3. K must be at a high level for outputs to transition.
4. Transition is measured
±
500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for
a given device.
AC SPEC LOADS
+5V
RL = 50
Ω
OUTPUT
Z0 = 50
Ω
VL = 1.5 V
OUTPUT
255
Ω
5 pF
480
Ω
Figure 1A
Figure 1B
MCM67D709
4
MOTOROLA FAST SRAM
READ CYCLE
(See Note)
tKHKH
tKLKH
K
tKLAX
tAVKL
A0 – A16
An
tKHPIEX
tPIEHKH
PIE
tKHSIEX
tSIEHKH
An + 1
An + 2
tKHKL
SIE
tKHWX
tWHKH
W
POE
tPOELQV
tPOELQX
SOE
tPOEHQZ
tPOEHQX
tSOELQV
PDQ0 – PDQ7, PDQP
tKHQV
SDQ0 – SDQ7, SDQP
Qn
tKHQX2
Qn + 1
Qn
tKHQX1
MOTOROLA FAST SRAM
MCM67D709
5
Embedded System
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