AVS
Technology
FEATURES
• Six Channel 24/20-bit DACs.
- 102 dB SNR
- 104 dB Dynamic Range.
- -90 dB THD + N Ratio.
- 32, 44.1 48 and 96 KHz. Sampling rates.
- 20-bit and 24-bit Digital Inputs.
- Containing Digital De-emphasis Filters.
- Digital Volume Control.
- I
2
S, Left and Right Justified Digital Input
Formats.
- Auto-Mute Control.
- On -chip Reconstruction Filters.
• Two Channel Stereo ADCs
- 32, 44.1 and 48 KHz. Sampling Rate.
- 100 dB SNR and Dynamic Range.
- -96 dB THD + N Ratio.
AV2188
Multi-Channel Audio CODEC
- I
2
S and Left Justified Output Formats.
• System clock: 384 fs for 32, 44.1 or 48 KH.
Sampling Rates, 194 fs for 96 KHz. Sam-
pling Rate.
General
• Automatic input format detection.
• 5-volt Power Supply.
• 3.3 -volt Digital Interface Frindly.
• I
2
C Interface for Mode Setting.
Applications
• Digital Surround Sound For Home Theater
• DVD
• Car Audio.
Ordering Information
• 28 pin SOJ package
SDA
SCL
80
I2C Serial
Control Port
AV2188
D/A
D/A
40KHz
40KHz
40KHz
40KHz
40KHz
40KHz
VOR3
VOL3
SD1
SD2
SD3
5th Order
Σ∆
Modulators
Digital Volume
De-Emphasis
96 Times
Over-sampling
Filters
80
D/A
D/A
D/A
D/A
VOR2
VOL2
VOR1
VOL1
Audio I/F
Serial
77
SDOUT
80
SF
SC
77
78
High Pass
Filter
Format
Detect'n
PLL
Decimation
Filter
A/D
A/D
BIN
AIN
15
XCK
RST
AVS Technology Inc.
4110 Clipper Ct., Fremont CA94538
Tel: (510) 353-0848
Fax: (510) 353-0856
1-20
June 2, 2000
AV2188
Item
PERFORMANCE SPECIFICATIONS
Audio DAC
Spec.
1
2
3
4
5
6
7
8
9
10
Audio Output Level
Audio Bandwidth 20Hz - 20 KHz
SNR (A-weight, Muted)
SNR (A-weight, Not Muted)
THD + N (A-weight, 0.5 FFS Output)
THD + N (A-weight, FFS Output)
Dynamic Range
Channel Separation
Nonlinear Distortion
Channel Gain Error
1 Vrms
+/- 0.5 dB
>102 dB
>96 dB
< -100 dB
< -92 dB
104 dB
< -97 dB
< 0.25 dB
< 0.1 dB
Audio ADC
1
2
2
3
4
4
Full Scale Audio Input Level
Maximum Input Level
Audio Bandwidth
SNR
THD + N (A-weight, 0.5 FFS Input)
Dynamic Range
1.5 V
p-p
5.0 V
p-p
20 KHz
98 dB
96 dB
98 dB
All Measurement were taken with only one channel active.
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June 2, 2000
AV2188
DESCRIPTION
The AV2188 is a mixed signal CMOS monolithic audio CODEC. It consists six channels sigma delta DACs and two
channels sigma delta ADCs. The DACs support 20-bit and 24-bit input data, while the ADCs provides 24-bit MSB
justified data output.
XCK REQUIREMENT
The AV2188 support 384 and 256 times sampling clock for 32, 44.1 and 48 K audio; 192 and 128 times for the 96
K audio.; and 96 and 64 times for the 192K audio. .
XCK Requirement
Sampling
Rate
32 K
44.1
48 K
96 K
192 K
XCK Freq.
384*fs
12.288 MHz
16.934 Mhz
18.432 MHz
18.432 MHz
18.432 Mhz
256*fs
8.192 MHz
11.29 Mhz.
12.288 Mhz.
12.288 Mhz.
12.288 Mhz.
3-20
June 2, 2000
AV2188
PIN ASSIGNMENT
SD1
SD2
SD3
SDOUT
SC
SF
DGND
DVDD
DGND
XCK
SCL
SDA
TST
RST
1
2
3
4
5
28
27
26
25
24
AR3
AL3
AR2
AL2
AR1
AL1
AGND
CM2
AVDD
CM1
AGND
RIN
LIN
N/C
A V 2 1 8 8
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
Pin Name
DIGITAL
SD1
SD2
SD3
SDOUT
SC
SF
1
2
3
4
5
6
I
I
I
O
I
I
Audio Serial Data Input 1, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
Audio Serial Data Input 2, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
Audio Serial Data Input 3, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
Serial Audio Output pin, data can be in 20bit Right justified or 20bit I2S format.
Audio Serial Data Clock pin.
Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in
SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For
I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right
Channel Data.
Digital ground
Digital power supply.
Pin #
Type
Description
DVSS
DVDD
7
8
GND
+5V
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June 2, 2000
AV2188
PIN DESCRIPTION (Continued)
Pin Name
DVSS
XCK
SCL
SDA
TEST
RST
Pin #
9
10
11
12
11
12
Type
GND
I
I
I/O
O
I
Digital ground
External Master Clock Input.
I2C clock input.
I2C DATA bus. Open drain ouput. Externally this pin should tie to a 680 ohm pull
up resistor.
Test fs reference pin. For test vector verification. For normal operation this pin
must be tied to ‘0’.
Active low power down reset. When low, the chip is reset and all programmable
registers are reset to default values. Must activate this pin if the P/S or
ADDR[1:0] change state.
Description
Analog
VOL3
VOR3
VOL2
VOR2
VOL1
VOR1
AVSS
VCM2
AVDD
VCM1
AVSS
AINR
AINL
N/C
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I
I
+5V
O
O
O
O
O
O
GND
Analog left channel output 3
Analog right channel output 3.
Analog left channel output 2.
Analog right channel output 2.
Analog left channel output 1.
Analog right channel output 1.
Analog circuits ground
Common voltage output pin for the DAC.
Analog circuits power supply
Common voltage output pin for the ADC.
Analog circuits ground
ADC right cahnnel input. 1 volt rms input.
ADC left channel input. 1 volt rms input.
No connection, should be tied to AVSS
5-20
June 2, 2000
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