MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM63P531/D
Advance Information
MCM63P531
32K x 32 Bit Pipelined BurstRAM™
Synchronous Fast Static RAM
The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the 68K Family, PowerPC™,
and Pentium™ microprocessors. It is organized as 32K words of 32 bits each,
fabricated using high performance silicon gate CMOS technology. This device
integrates input registers, an output register, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power consump-
tion of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output en-
able (G) and Linear Burst Order (
LBO
) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P531 (burst sequence op-
erates in linear or interleaved mode dependent upon state of LBO) and controlled
by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P531 operates from a 3.3 V power supply, all inputs and outputs
are LVTTL compatible.
•
MCM63P531–4.5 = 4.5 ns access / 10 ns cycle
MCM63P531–7 = 7 ns access / 13.3 ns cycle
MCM63P531–8 = 8 ns access / 15 ns cycle
MCM63P531–9 = 9 ns access / 16.6 ns cycle
•
Single 3.3 V + 10%, – 5% Power Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
Sleep Mode (ZZ)
•
Intel PBSRAM 2.0 Compliant
•
Single–Cycle Deselect Timing
•
100 Pin TQFP Package
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
TQ PACKAGE
TQFP
CASE 983A–01
6/21/96
©
Motorola, Inc. 1996
MOTOROLA FAST SRAM
MCM63P531
1
PIN DESCRIPTIONS
Pin Locations
85
84
Symbol
ADSC
ADSP
Type
Input
Input
Description
Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle.
Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
83
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29
86
ADV
DQx
Input
I/O
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high–blocks ADSP or deselects chip when ADSC is asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
Power Supply: 3.3 V + 10%, – 5%.
Ground.
No Connection: There is no connection to the chip.
89
31
K
LBO
Input
Input
32, 33, 34, 35, 44, 45, 46,
47, 48, 81, 82, 99, 100
36, 37
SA
SA1,SA0
Input
Input
93, 94, 95, 96
(a) (b) (c) (d)
98
97
92
88
SBx
SE1
SE2
SE3
SGW
Input
Input
Input
Input
Input
87
SW
Input
64
ZZ
Input
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
5, 10, 17, 21, 26, 40, 55,
60, 67, 71, 76, 90
1, 14, 16, 30, 38, 39, 42, 43, 49,
50, 51, 66, 80
VDD
VSS
NC
Supply
Supply
—
MCM63P531
4
MOTOROLA FAST SRAM
Analog electronics
京公网安备 11010802033920号
EEWORLD
