MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6265C/D
8K x 9 Bit Fast Static RAM
The MCM6265C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 12, 15, 20, 25, and 35 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
•
Low Power Operation: 110 – 150 mA Maximum AC
•
Fully TTL Compatible — Three State Output
•
•
•
•
•
MCM6265C
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
A8
A7
A6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
E2
A9
A10
A11
G
A12
E1
DQ8
DQ7
DQ6
DQ5
DQ4
BLOCK DIAGRAM
A2
A3
A4
A5
A7
A9
A10
A11
DQ0
INPUT
DATA
CONTROL
DQ8
COLUMN I/O
COLUMN DECODER
ROW
DECODER
MEMORY MATRIX
256 ROWS x 32
x 9 COLUMNS
VCC
VSS
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
A0 A1 A6
A8 A12
PIN NAMES
A0 – A12 . . . . . . . . . . . . . Address Input
DQ0 – DQ8 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
E1
E2
W
G
REV 2
5/95
©
Motorola, Inc. 1994
MOTOROLA FAST SRAM
MCM6265C
1
TRUTH TABLE
(X = Don’t Care)
E1
H
X
L
L
L
E2
X
L
H
H
H
G
X
X
H
L
X
W
X
X
H
H
L
Mode
Not Selected
Not Selected
Output Disabled
Read
Write
VCC Current
ISB1, ISB2
ISB1, ISB2
ICCA
ICCA
ICCA
Output
High–Z
High–Z
High–Z
Dout
High–Z
Cycle
—
—
—
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Output Current
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
Symbol
VCC
Vin, Vout
Iout
PD
Tbias
TA
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
±
20
1.0
– 10 to + 85
0 to + 70
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns)
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width
≤
20 ns)
Symbol
VCC
VIH
VIL
Min
4.5
2.2
– 0.5*
Typ
5.0
—
—
Max
5.5
VCC + 0.3**
0.8
Unit
V
V
V
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (E1 = VIH, E2 = VIL, or G = VIH, Vout = 0 to VCC)
Output Low Voltage (IOL = 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
Symbol
Ilkg(I)
Ilkg(O)
VOL
VOH
Min
—
—
—
2.4
Max
±
1
±
1
0.4
—
Unit
µA
µA
V
V
POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax)
AC Standby Current (E1 = VIH or E2 = VIL, VCC = Max, f = fmax)
Standby Current (E1
≥
VCC – 0.2 V or E2
≤
VSS + 0.2 V,
Vin
≤
VSS + 0.2 V or
≥
VCC – 0.2 V)
Symbol
ICCA
ISB1
ISB2
– 12
150
45
20
– 15
140
40
20
– 20
130
35
20
– 25
120
30
20
– 35
110
30
20
Unit
mA
mA
mA
CAPACITANCE
(f = 1 MHz, dV = 3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Address Input Capacitance
Control Pin Input Capacitance (E1, E2, G, W)
I/O Capacitance
Symbol
Cin
Cin
CI/O
Max
6
6
7
Unit
pF
pF
pF
MCM6265C
2
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE
(See Notes 1 and 2)
– 12
Parameter
Read Cycle Time
Address Access Time
Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Enable High to Output High–Z
Output Enable Low to Output Active
Output Enable High to Output High–Z
Power Up Time
Power Down Time
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
Min
12
—
—
—
4
4
0
0
0
0
—
Max
—
12
12
6
—
—
6
—
6
—
12
– 15
Min
15
—
—
—
4
4
0
0
0
0
—
Max
—
15
15
8
—
—
8
—
7
—
15
– 20
Min
20
—
—
—
4
4
0
0
0
0
—
Max
—
20
20
10
—
—
9
—
8
—
20
– 25
Min
25
—
—
—
4
4
0
0
0
0
—
Max
—
25
25
11
—
—
10
—
9
—
25
– 35
Min
35
—
—
—
4
4
0
0
0
0
—
Max
—
35
35
12
—
—
11
—
10
—
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5,6,7
5,6,7
5,6,7
5,6,7
4
Notes
3
NOTES:
1. W is high for read cycle.
2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given
device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL).
AC TEST LOADS
+5V
OUTPUT
Z0 = 50
Ω
50
Ω
VL = 1.5 V
OUTPUT
255
Ω
5 pF
480
Ω
TIMING LIMITS
The table of timing values shows either
a minimum or a maximum limit for each pa-
rameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a maxi-
mum since the device never provides data
later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6265C
3
READ CYCLE 1
(See Note 8)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
tAVQV
DATA VALID
READ CYCLE 2
(See Note 4)
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGLQV
tGLQX
Q (DATA OUT)
HIGH–Z
DATA VALID
tEHICCL
HIGH–Z
tGHQZ
VCC
SUPPLY
CURRENT
ICC
ISB
tELICCH
MCM6265C
4
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
– 12
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Pulse Width, G High
Data Valid to End of Write
Data Hold Time
Write Low to Output High–Z
Write High to Output Active
Write Recovery Time
Symbol
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
tWLWH,
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Min
12
0
10
10
8
6
0
0
4
0
Max
—
—
—
—
—
—
—
6
—
—
– 15
Min
15
0
12
12
10
7
0
0
4
0
Max
—
—
—
—
—
—
—
7
—
—
– 20
Min
20
0
15
15
12
8
0
0
4
0
Max
—
—
—
—
—
—
—
8
—
—
– 25
Min
25
0
17
17
15
10
0
0
4
0
Max
—
—
—
—
—
—
—
10
—
—
– 35
Min
35
0
20
20
17
12
0
0
4
0
Max
—
—
—
—
—
—
—
12
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 7, 8
6, 7, 8
5
Notes
4
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G
≥
VIH, the output will remain in a high impedance state.
6. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
7. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
tAVAV
A (ADDRESS)
tAVWH
E (CHIP ENABLE)
tWLWH
tWLEH
W (WRITE ENABLE)
tAVWL
D (DATA IN)
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tDVWH
DATA VALID
tWHQX
tWHDX
tWHAX
MOTOROLA FAST SRAM
MCM6265C
5
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