HD74CDCF2510B
140 MHz, 0 to 85°C Operation
3.3-V Phase-lock Loop Clock Driver
ADE-205-225F (Z)
7th. Edition
January 2000
Description
The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDCF2510B operates at 3.3 V V
CC
and is designed to drive up to five clock loads per output.
Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are
adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or
disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency
with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDCF2510B does not require external RC networks.
The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDCF2510B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV
CC
to ground.
Features
•
•
•
•
•
•
•
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
Phase-lock loop clock distribution for synchronous DRAM applications
External feedback (FBIN) pin is used to synchronize the outputs to the clock input
No external RC network required
Support spread spectrum clock (SSC) synthesizers
Supports frequencies up to 140 MHz
0 to 85°C operating range
HD74CDCF2510B
Function Table
Inputs
G
X
L
H
H:
L:
X:
High level
Low level
Immaterial
CLK
L
H
H
Outputs
1Y (0:9)
L
L
H
FBOUT
L
H
H
Pin Arrangement
AGND 1
V
CC
2
24 CLK
23 AV
CC
22 V
CC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 V
CC
13 FBIN
1Y0 3
1Y1 4
1Y2 5
GND
6
GND 7
1Y3 8
1Y4
9
V
CC
10
G 11
FBOUT 12
(Top view)
2
HD74CDCF2510B
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
T
stg
Ratings
–0.5 to 4.6
–0.5 to 6.5
Unit
V
V
Conditions
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
Supply current
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
–0.5 to V
CC
+0.5 V
–50
±50
±50
±100
0.7
–65 to +150
mA
mA
mA
mA
W
°C
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and
a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Symbol Min
V
CC
V
IH
V
IL
V
I
Output current
I
O H
I
O L
Operating temperature
T
a
3.0
2.0
—
0
—
—
0
Typ
—
—
—
—
—
—
—
Max
3.6
—
0.8
V
CC
–12
12
85
°C
mA
Unit
V
V
Conditions
Note: Unused inputs must be held high or low to prevent them from floating.
3
HD74CDCF2510B
Logic Diagram
G
11
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
FBOUT
15
16
17
CLK
FBIN
AV
CC
24
20
PLL
13
21
23
12
4
HD74CDCF2510B
Pin Function
Pin name
CLK
No.
24
Type
I
Description
Clock input. CLK provides the clock signal to be distributed by the
HD74CDCF2510B clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase
for the PLL to obtain phase lock. Once the circuit is powered up
and a valid CLK signal is applied, a stabilization time is required for
the PLL to phase lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9).
When G is low, outputs 1Y(0:9)are disabled to a logic-low state.
When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 1Y(0:9) is enabled via the G input. These outputs can
be disabled to a logic low state by deasserting the G control input.
Analog power supply. AV
CC
provides the power reference for the
analog circuitry. In addition, AV
CC
can be used to bypass the PLL
for test purposes. When AV
CC
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
FBIN
13
I
G
11
I
FBOUT
12
O
1Y(0:9)
3, 4, 5, 8, 9, O
15, 16, 17,
20, 21
23
Power
AV
CC
AGND
V
CC
GND
1
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
Power supply
2, 10, 14, 22 Power
6, 7, 18,19
Ground Ground
5
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