Circuit diagram for controlling charge and discharge of absorption capacitor

　　In the circuit shown in Figure (a), VF1 is the primary side main MOSFET, and the pulses from the PWM integrated controller

　　After VF1 is cut off, the current of the secondary side diode VD2 drops to zero, and the transformer has no excitation energy. At this time, the flyback voltage induced by the primary winding N1 becomes zero, and the absorption capacitor C1, which is charged with a voltage higher than the voltage on C1, reversely discharges the primary primary winding N1. In this way, the discharge current passes through the parasitic diode of VF2 (shown by the dotted line) circulation. When Cr discharge starts, VF2 must be cut off. Due to the discharge of Cr, the capacitor Cr resonates with the inductance Lp of the primary winding .

　　(a) Principle circuit (b) Practical circuit

Circuit diagram　　for controlling the charging and discharging of the absorption capacitor

　　If VF2 is in the conductive state, the resonance continues to attenuate and oscillate, but when VF2 is in the off state, the oscillation stops when the voltage across the capacitor Cr reaches zero. If Cr stops resonating, the smaller capacitance input capacitors of VF1 and VF2 will continue to produce a shorter period of resonance . When VF1 is turned on again, the small capacitor discharge current flows through VF1 itself and is consumed. When VF1 is turned on, the voltage charged by its small-capacity capacitor changes with the turn-on time, but the voltage across Cr drops to the lowest voltage. Therefore, the loss caused by Cr can be reduced. In other words, even if a larger capacity capacitor Cr is used, the Cr loss will not increase.

　　Figure (a) shows a circuit using a VF2 parasitic diode to discharge Cr. The recovery characteristics of general MOS-FET parasitic diodes are not suitable for high frequencies. Therefore, a low-loss diode is added as a capacitor discharge diode, that is, the diode VD1 in Figure (b). In order to make all the discharge current flow through the diode VD1, a reverse blocking diode VD2 is added to the VF2 circuit. The withstand voltage of the reverse blocking diode VD2 only needs to be greater than the forward voltage drop of VD1. Therefore, a Schottky diode (SBD) is selected. . In addition, the bidirectional delay element should use a saturable reactor. The delay element and the input capacitance of YF2 jointly determine the delay time. When a longer delay time is required, a capacitor can be added to the gate. As the output current decreases, the conduction time of VF1 becomes shorter. If the conduction time is shorter than the delay time, VF2 will be turned on after VF1 is turned off. Therefore, the waveform of the voltage UDS between the drain and the source of VF1 deviates from the normal waveform, and the power consumption is also slightly increased. In order to reduce the minimum output current, the delay time must be very short, so that the capacitor Cr cannot be fully utilized. Here, as a rough target, the minimum output current is set to 2% to 3% of the maximum output current.