PRODUCT BRIEF
19-5785; Rev 2; 3/11
DS3170
DS3/E3 Single-Chip Transceiver
GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
FEATURES
Single-Chip Transceiver for DS3 and E3
Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
Interfaces to 75Ω Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
Uses 1:2 Transformers on Both Tx and Rx
On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
Software Compatible with DS3171–DS3174 SCT
Product Family
8-/16-Bit Parallel and Slave SPI Serial (
≤ 10Mbps)
Microprocessor Interface
Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
100-Pin Small 11mm x 11mm (1mm) CSBGA
Industrial Temperature Operation: -40°C to +85°C
IEEE 1149.1 JTAG Test Port
APPLICATIONS
Access Concentrators
Routers and Switches
SONET/SDH ADM
SONET/SDH Muxes
PBXs
PDH Multiplexer/
Demultiplexer
Multiservice Access
Platforms (MSAPs)
Multiservice Protocol
Platform (MSPPs)
Test Equipment
Digital Cross Connect
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART
DS3170
DS3170+
DS3170N
DS3170N+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
100 CSBGA
100 CSBGA
100 CSBGA
100 CSBGA
+Denotes a lead(Pb)-free/RoHS compliant package.
FUNCTIONAL DIAGRAM
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
DS3/E3 LINE
DS3170
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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DS3170 DS3/E3 Single-Chip Transceiver
TABLE OF CONTENTS
1
2
3
4
DETAILED DESCRIPTION
BLOCK DIAGRAMS
APPLICATIONS
FEATURE DETAILS
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
10
10
12
13
G
LOBAL
F
EATURES
.................................................................................................................................. 13
R
ECEIVE
DS3/E3 LIU F
EATURES
.............................................................................................................. 13
J
ITTER
A
TTENUATOR
F
EATURES
................................................................................................................ 13
R
ECEIVE
DS3/E3 F
RAMER
F
EATURES
....................................................................................................... 13
T
RANSMIT
DS3/E3 F
ORMATTER
F
EATURES
................................................................................................ 14
T
RANSMIT
DS3/E3 LIU F
EATURES
............................................................................................................ 14
C
LOCK
R
ATE
A
DAPTER
F
EATURES
............................................................................................................. 14
HDLC C
ONTROLLER
F
EATURES
................................................................................................................ 14
FEAC C
ONTROLLER
F
EATURES
................................................................................................................ 14
T
RAIL
T
RACE
B
UFFER
F
EATURES
.............................................................................................................. 15
B
IT
E
RROR
-R
ATE
T
ESTER
(BERT) F
EATURES
............................................................................................ 15
L
OOPBACK
F
EATURES
.............................................................................................................................. 15
M
ICROPROCESSOR
I
NTERFACE
F
EATURES
................................................................................................. 15
S
LAVE
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) F
EATURES
............................................................................. 15
T
EST
F
EATURES
...................................................................................................................................... 15
5
6
7
STANDARDS COMPLIANCE
ACRONYMS AND GLOSSARY
MAJOR OPERATIONAL MODES
7.1
7.2
7.3
7.4
7.5
7.6
16
17
18
DS3/E3 F
RAMED
LIU M
ODE
..................................................................................................................... 18
DS3/E3 U
NFRAMED
LIU M
ODE
................................................................................................................. 20
DS3/E3 F
RAMED
POS/NEG M
ODE
........................................................................................................... 21
DS3/E3 U
NFRAMED
POS/NEG M
ODE
...................................................................................................... 22
DS3/E3 F
RAMED
UNI M
ODE
.................................................................................................................... 23
DS3/E3 U
NFRAMED
UNI M
ODE
................................................................................................................ 24
8
PIN DESCRIPTIONS
25
8.1 S
HORT
P
IN
D
ESCRIPTIONS
........................................................................................................................ 25
8.2 D
ETAILED
P
IN
D
ESCRIPTIONS
.................................................................................................................... 27
8.3 P
IN
F
UNCTIONAL
T
IMING
........................................................................................................................... 37
8.3.1 Line IO ............................................................................................................................................ 37
8.3.2 DS3/E3 Framing Overhead Functional Timing ................................................................................. 40
8.3.3 DS3/E3 Serial Data Interface .......................................................................................................... 41
8.3.4 Microprocessor Interface Functional Timing .................................................................................... 43
8.3.5 JTAG Functional Timing .................................................................................................................. 50
9
10
INITIALIZATION AND CONFIGURATION
9.1
51
53
M
ONITORING AND
D
EBUGGING
.................................................................................................................. 52
FUNCTIONAL DESCRIPTION
10.1 P
ROCESSOR
B
US
I
NTERFACE
.................................................................................................................... 53
10.1.1 SPI Serial Port Mode....................................................................................................................... 53
10.1.2 8/16 Bit Bus Widths......................................................................................................................... 53
10.1.3 Ready Signal (
RDY
) ........................................................................................................................ 53
10.1.4 Byte Swap Modes ........................................................................................................................... 53
10.1.5 Read-Write/Data Strobe Modes....................................................................................................... 53
10.1.6 Clear on Read/Clear on Write Modes .............................................................................................. 53
10.1.7 Interrupt and Pin Modes .................................................................................................................. 54
10.1.8 Interrupt Structure ........................................................................................................................... 54
10.2 C
LOCKS
.................................................................................................................................................. 55
10.2.1 Line Clock Modes ........................................................................................................................... 55
10.2.2 Sources of Clock Output Pin Signals ............................................................................................... 57
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DS3170 DS3/E3 Single-Chip Transceiver
10.2.3 Line IO Pin Timing Source Selection ............................................................................................... 59
10.2.4 Clock Structures On Signal IO Pins ................................................................................................. 62
10.2.5 Gapped Clocks ............................................................................................................................... 63
10.3 R
ESET AND
P
OWER
-D
OWN
....................................................................................................................... 63
10.4 G
LOBAL
R
ESOURCES
............................................................................................................................... 66
10.4.1 Clock Rate Adapter (CLAD) ............................................................................................................ 66
10.4.2 8 kHz Reference Generation ........................................................................................................... 66
10.4.3 One Second Reference Generation................................................................................................. 67
10.4.4 General-Purpose IO Pins ................................................................................................................ 68
10.4.5 Performance Monitor Counter Update Details ................................................................................. 69
10.4.6 Transmit Manual Error Insertion ...................................................................................................... 70
10.5 P
ORT
R
ESOURCES
................................................................................................................................... 71
10.5.1 Loopbacks ...................................................................................................................................... 71
10.5.2 Loss Of Signal Propagation ............................................................................................................. 73
10.5.3 AIS Logic ........................................................................................................................................ 73
10.5.4 Loop Timing Mode .......................................................................................................................... 75
10.5.5 HDLC Overhead Controller ............................................................................................................. 75
10.5.6 Trail Trace ...................................................................................................................................... 75
10.5.7 BERT .............................................................................................................................................. 75
10.5.8 System Port Pins ............................................................................................................................ 76
10.5.9 Framing Modes ............................................................................................................................... 77
10.5.10 Line Interface Modes....................................................................................................................... 77
10.6 DS3/E3 F
RAMER
/ F
ORMATTER
................................................................................................................. 79
10.6.1 General Description ........................................................................................................................ 79
10.6.2 Features ......................................................................................................................................... 79
10.6.3 Transmit Formatter ......................................................................................................................... 80
10.6.4 Receive Framer .............................................................................................................................. 80
10.6.5 C-bit DS3 Framer/Formatter ............................................................................................................ 84
10.6.6 M23 DS3 Framer/Formatter ............................................................................................................ 87
10.6.7 G.751 E3 Framer/Formatter ............................................................................................................ 89
10.6.8 G.832 E3 Framer/Formatter ............................................................................................................ 91
10.7 HDLC O
VERHEAD
C
ONTROLLER
............................................................................................................... 96
10.7.1 General Description ........................................................................................................................ 96
10.7.2 Features ......................................................................................................................................... 97
10.7.3 Transmit FIFO................................................................................................................................. 97
10.7.4 Transmit HDLC Overhead Processor .............................................................................................. 98
10.7.5 Receive HDLC Overhead Processor ............................................................................................... 98
10.7.6 Receive FIFO.................................................................................................................................. 99
10.8 T
RAIL
T
RACE
C
ONTROLLER
....................................................................................................................... 99
10.8.1 General Description ........................................................................................................................ 99
10.8.2 Features ....................................................................................................................................... 100
10.8.3 Functional Description................................................................................................................... 100
10.8.4 Transmit Data Storage .................................................................................................................. 101
10.8.5 Transmit Trace ID Processor......................................................................................................... 101
10.8.6 Transmit Trail Trace Processing .................................................................................................... 101
10.8.7 Receive Trace ID Processor.......................................................................................................... 101
10.8.8 Receive Trail Trace Processing ..................................................................................................... 101
10.8.9 Receive Data Storage ................................................................................................................... 102
10.9 FEAC C
ONTROLLER
.............................................................................................................................. 102
10.9.1 General Description ...................................................................................................................... 102
10.9.2 Features ....................................................................................................................................... 103
10.9.3 Functional Description................................................................................................................... 103
10.10 L
INE
E
NCODER
/D
ECODER
....................................................................................................................... 104
10.10.1 General Description ...................................................................................................................... 104
10.10.2 Features ....................................................................................................................................... 105
10.10.3 B3ZS/HDB3 Encoder .................................................................................................................... 105
10.10.4 Transmit Line Interface ................................................................................................................. 105
10.10.5 Receive Line Interface .................................................................................................................. 106
10.10.6 B3ZS/HDB3 Decoder .................................................................................................................... 106
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DS3170 DS3/E3 Single-Chip Transceiver
10.11 BERT .................................................................................................................................................. 108
10.11.1 General Description ...................................................................................................................... 108
10.11.2 Features ....................................................................................................................................... 108
10.11.3 Configuration and Monitoring ........................................................................................................ 108
10.11.4 Receive Pattern Detection............................................................................................................. 109
10.11.5 Transmit Pattern Generation ......................................................................................................... 111
10.12 LIU – L
INE
I
NTERFACE
U
NIT
.................................................................................................................... 112
10.12.1 General Description ...................................................................................................................... 112
10.12.2 Features ....................................................................................................................................... 112
10.12.3 Detailed Description ...................................................................................................................... 112
10.12.4 Transmitter ................................................................................................................................... 113
10.12.5 Receiver ....................................................................................................................................... 114
11
12
OVERALL REGISTER MAP
REGISTER MAPS AND DESCRIPTIONS
117
119
12.1 R
EGISTERS
B
IT
M
APS
............................................................................................................................ 119
12.1.1 Global Register Bit Map ................................................................................................................ 119
12.1.2 HDLC Register Bit Map ................................................................................................................. 121
12.1.3 T3 Register Bit Map ...................................................................................................................... 123
12.1.4 E3 G.751 Register Bit Map............................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map............................................................................................................ 125
12.2 G
LOBAL
R
EGISTERS
............................................................................................................................... 126
12.2.1 Register Bit Descriptions ............................................................................................................... 126
12.3 P
ORT
R
EGISTER
.................................................................................................................................... 133
12.3.1 Register Bit Descriptions ............................................................................................................... 133
12.4 BERT .................................................................................................................................................. 144
12.4.1 BERT Register Map ...................................................................................................................... 144
12.4.2 BERT Register Bit Descriptions ..................................................................................................... 144
12.5 B3ZS/HDB3 L
INE
E
NCODER
/D
ECODER
................................................................................................... 151
12.5.1 Transmit Side Line Encoder/Decoder Register Map ...................................................................... 151
12.5.2 Receive Side Line Encoder/Decoder Register Map ....................................................................... 152
12.6 HDLC .................................................................................................................................................. 156
12.6.1 HDLC Transmit Side Register Map................................................................................................ 156
12.6.2 HDLC Receive Side Register Map ................................................................................................ 159
12.7 FEAC C
ONTROLLER
.............................................................................................................................. 163
12.7.1 FEAC Transmit Side Register Map................................................................................................ 163
12.7.2 FEAC Receive Side Register Map................................................................................................. 165
12.8 T
RAIL
T
RACE
......................................................................................................................................... 168
12.8.1 Trail Trace Transmit Side .............................................................................................................. 168
12.8.2 Trail Trace Receive Side Register Map ......................................................................................... 169
12.9 DS3/E3
FRAMER
................................................................................................................................... 174
12.9.1 Transmit DS3 ................................................................................................................................ 174
12.9.2 Receive DS3 Register Map ........................................................................................................... 176
12.9.3 Transmit G.751 E3 ........................................................................................................................ 183
12.9.4 Receive G.751 E3 Register Map ................................................................................................... 186
12.9.5 Transmit G.832 E3 Register Map .................................................................................................. 191
12.9.6 Receive G.832 E3 Register Map ................................................................................................... 194
13
JTAG INFORMATION
202
13.1
13.2
13.3
13.4
13.5
13.6
JTAG D
ESCRIPTION
............................................................................................................................... 202
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
.......................................................................... 203
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
................................................................................... 205
JTAG ID C
ODES
................................................................................................................................... 206
JTAG F
UNCTIONAL
T
IMING
..................................................................................................................... 207
IO P
INS
................................................................................................................................................ 207
14
15
16
PIN CONFIGURATIONS
DC ELECTRICAL CHARACTERISTICS
AC TIMING CHARACTERISTICS
4 of 230
208
211
213
DS3170 DS3/E3 Single-Chip Transceiver
16.1 F
RAMER
D
ATA
P
ATH
AC C
HARACTERISTICS
............................................................................................. 215
16.2 O
VERHEAD
P
ORT
AC C
HARACTERISTICS
.................................................................................................. 216
16.3 M
ICRO
I
NTERFACE
AC C
HARACTERISTICS
................................................................................................ 217
16.3.1 SPI Bus Mode ............................................................................................................................... 217
16.3.2 Parallel Bus Mode ......................................................................................................................... 219
16.4 CLAD J
ITTER
C
HARACTERISTICS
............................................................................................................ 222
16.5 LIU I
NTERFACE
AC C
HARACTERISTICS
..................................................................................................... 222
16.5.1 Waveform Templates .................................................................................................................... 222
16.5.2 LIU Input/Output Characteristics.................................................................................................... 225
16.6 JTAG I
NTERFACE
AC C
HARACTERISTICS
................................................................................................. 227
17
18
19
PACKAGE INFORMATION
THERMAL INFORMATION
REVISION HISTORY
228
229
230
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