DS1267E-100- datasheet, PDF - EEWORLD Datasheet

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DS1267E-100-: DescriptionDigital Potentiometer ICs Dual +/-5V; Categorysemiconductor Other integrated circuit (IC); File Size311KB，12 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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Digital Potentiometer ICs Dual +/-5V

DS1267E-100- Parametric

Parameter Name	Attribute value
Product Category	Digital Potentiometer ICs
Manufacturer	Maxim
RoHS	Details
Resistance	100 kOhms
Number of POTs	Dual
Taps per POT	256
Wiper Memory	Volatile
Digital Interface	Serial (3-Wire)
Operating Supply Voltage	5 V
Operating Supply Current	650 uA
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	TSSOP-20
Packaging	Tube
Height	0.9 mm
Length	6.5 mm
Minimum Operating Temperature	- 40 C
Factory Pack Quantity	74
Supply Type	Single, Dual
Supply Voltage - Max	5.5 V
Supply Voltage - Min	4.5 V
Taper	Linear
Width	4.4 mm
Unit Weight	0.006737 oz

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DS1267

Dual Digital Potentiometer Chip

www.dalsemi.com

FEATURES

Ultra-low power consumption, quiet,

pumpless design

Two digitally controlled, 256-position

potentiometers

Serial port provides means for setting and

reading both potentiometers

Resistors can be connected in series to

provide increased total resistance

14-pin DIP, 16-pin SOIC, 20-pin TSSOP

packages

Resistive elements are temperature

compensated to ±0.3 LSB relative linearity

Standard resistance values:

– DS1267-10 ~ 10 kΩ

– DS1267-50 ~ 50 kΩ

– DS1267-100 ~ 100 kΩ

Operating Temperature Range:

– Industrial: -40°C to +85°C

PIN ASSIGNMENT

RST

CLK

GND

OUT

16-Pin SOIC (300-mil)

See Mech. Drawings Section

OUT

PIN DESCRIPTIONS

L0, L1

H0, H1

W0, W1

OUT

RST

CLK

OUT

GND

Low End of Resistor

High End of Resistor

Wiper Terminal of Resistor

Substrate Bias Voltage

Stacked Configuration Output

Serial Port Reset Input

Serial Port Data Input

Serial Port Clock Input

Cascade Port Output

+5 Volt Supply

Ground

No Internal Connection

RST

CLK

GND

14-Pin DIP (300-mil)

See Mech. Drawings Section

RST

CLK

GND

OUT

20-Pin TSSOP (173-mil)

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DS1267

DESCRIPTION

The DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state

potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section

and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the

wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper

output. Communication and control of the device are accomplished via a 3-wire serial port interface.

This interface allows the device wiper position to be read or written.

Both potentiometers can be connected in series (or stacked) for an increased total resistance with the

same resolution. For multiple-device, single-processor environments, the DS1267 can be cascaded or

daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus.

The DS1267 is offered in three standard resistance values which include 10, 50, and 100-kohm versions.

Available packages for the device include a 14-pin DIP, 16-pin SOIC, and 20-pin TSSOP.

OPERATION

The DS1267 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.

These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions

and the stack select bit when the device is powered. A block diagram of the DS1267 is presented in

Figure 1.

Communication and control of the DS1267 are accomplished through a 3-wire serial port interface that

drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:

RST

CLK, and DQ.

The

RST

control signal is used to enable the 3-wire serial port operation of the device. The chip is

selected when

RST

is high;

RST

must be high to begin any communication to the DS1267. The CLK

signal input is used to provide timing synchronization for data input and output. The DQ signal line is

used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift

Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the

RST

signal input is low. Communication with the DS1267 requires the transition of the

RST

input from a low

state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to

high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing

diagrams of Figure 9(b)-(c).

Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see

Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the

stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift

Configuration." Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.

Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting.

Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the

MSB for the wiper position occupying bit 9 and the LSB bit 16.

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102199

DS1267

The C

OUT

output of the DS1267 can be used to drive the DQ input of another DS1267. When connecting

multiple devices, the total number of bits transmitted is always 17 times the number of DS1267s in the

daisy chain.

An optional feedback resistor can be placed between the C

OUT

terminal of the last device and the first

DS1267 DQ input, thus allowing the controlling processor to read as well as write data or circularly clock

data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1

to 10 kohms.

When reading data via the C

OUT

pin and isolation resistor, the DQ line is left floating by the reading

device. When

RST

is driven high, bit 17 is present on the C

OUT

pin, which is fed back to the input DQ

pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the

first position of the I/O shift register and bit 16 becomes present on C

OUT

and DQ of the next device. After

17 bits (or 17 times the number of DS1267s in the daisy chain), the data has shifted completely around

and back to its original position. When

RST

transitions to the low state to end data transfer, the value (the

same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.

ABSOLUTE AND RELATIVE LINEARITY

Absolute linearity is defined as the difference between the actual measured output voltage and the

expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute

linearity is given in terms of a minimum increment or expected output when the wiper is moved one

position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 10/512 volts.

The equation for absolute linearity is given as follows:

(1)

ABSOLUTE LINEARITY

AL={V

(actual) - V

(expected)}/MI

Relative Linearity is a measure of error between two adjacent wiper position points and is given in terms

of MI by equation (2).

(2)

RELATIVE LINEARITY

RL={V

(n+1) - V

(n)}/MI

Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25°C.

The specification for absolute linearity of the DS1267 is ±0.75 MI typical. The specification for relative

linearity of the DS1267 is ±0.3 MI typical.

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102199

DS1267E-100- Related Products

	DS1267E-100-	DS1267E-50-TR	DS1267S-010-	DS1267-010-	DS1267E-100-TR	DS1267-010	DS1267E-10	DS1267S-100-	DS1267S-010-TR
Description	Digital Potentiometer ICs Dual +/-5V	Digital Potentiometer ICs Dual +/-5V	Digital Potentiometer ICs Dual +/-5V	Digital Potentiometer ICs Dual +/-5V	Digital Potentiometer ICs	Digital Potentiometer ICs DS1267-010	Digital Potentiometer ICs	Digital Potentiometer ICs Dual +/-5V	Digital Potentiometer ICs Dual +/-5V
Product Category	Digital Potentiometer ICs	Digital Potentiometer ICs	Digital Potentiometer ICs	Digital Potentiometer ICs	Digital Potentiometer ICs	Digital Potentiometer ICs	-	Digital Potentiometer ICs	Digital Potentiometer ICs
Manufacturer	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim	-	Maxim	Maxim
RoHS	Details	Details	Details	Details	-	No	-	Details	Details
Resistance	100 kOhms	50 kOhms	10 kOhms	10 kOhms	100 kOhms	10 kOhms	-	100 kOhms	10 kOhms
Number of POTs	Dual	Dual	Dual	Dual	Dual	Dual	-	Dual	Dual
Taps per POT	256	256	256	256	256	256	-	256	256
Wiper Memory	Volatile	Volatile	Volatile	Volatile	Volatile	Volatile	-	Volatile	Volatile
Digital Interface	Serial (3-Wire)	Serial (3-Wire)	Serial (3-Wire)	Serial (3-Wire)	Serial (3-Wire)	Serial (3-Wire)	-	Serial (3-Wire)	Serial (3-Wire)
Operating Supply Voltage	5 V	5 V	4.5 V to 5.5 V	4.5 V to 5.5 V	5 V	5 V	-	4.5 V to 5.5 V	5 V
Operating Supply Current	650 uA	650 uA	22 uA	22 uA	650 uA	650 uA	-	22 uA	650 uA
Maximum Operating Temperature	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 85 C	-	+ 85 C	+ 85 C
Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	Through Hole	SMD/SMT	Through Hole	-	SMD/SMT	SMD/SMT
Package / Case	TSSOP-20	TSSOP-20	SOIC-16	PDIP-14	TSSOP-20	PDIP-Narrow-14	-	SOIC-16	SOIC-Wide-16
Packaging	Tube	Cut Tape	Tube	Tube	-	-	-	Tube	Reel
Height	0.9 mm	0.9 mm	2.65 mm	4.572 mm	0.9 mm	4.45 mm	-	2.65 mm	2.35 mm
Length	6.5 mm	6.5 mm	10.5 mm	19.43 mm	6.5 mm	19.43 mm	-	10.5 mm	10.5 mm
Minimum Operating Temperature	- 40 C	- 40 C	- 40 C	- 40 C	- 40 C	- 40 C	-	- 40 C	- 40 C
Factory Pack Quantity	74	2500	46	25	-	25	-	45	1000
Supply Type	Single, Dual	Single, Dual	Dual	Dual	Single, Dual	Single, Dual	-	Dual	Single, Dual
Supply Voltage - Max	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	-	5.5 V	5.5 V
Supply Voltage - Min	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	-	4.5 V	4.5 V
Taper	Linear	Linear	Linear	Linear	Linear	Linear	-	Linear	Linear
Width	4.4 mm	4.4 mm	7.6 mm	8.26 mm	4.4 mm	7.87 mm	-	7.6 mm	7.6 mm
Unit Weight	0.006737 oz	0.006737 oz	0.023492 oz	0.057144 oz	0.006737 oz	-	-	0.023492 oz	0.016709 oz

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