or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1001 Introduction_01.5
Lattice Semiconductor
Introduction
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
The ispLEVER
®
design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
LatticeXP Family Data Sheet
Architecture
July 2007
Data Sheet DS1001
Architecture Overview
The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-
1.
On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this non-
volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,
the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this
technology, expensive external configuration memories are not required and designs are secured from unauthor-
ized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in
microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeXP architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from
3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1001
Architecture_02.0
Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
Programmable I/O Cell
(PIC) includes sysIO
Interface
Architecture
LatticeXP Family Data Sheet
sysMEM Embedded
Block RAM (EBR)
Non-volatile Memory
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
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