ispClock 5300S Family
™
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
October 2007
Preliminary Data Sheet DS1010
Features
■
Four Operating Configurations
•
•
•
•
Zero delay buffer
Zero delay and non-zero delay buffer
Dual non-zero delay buffer
Non-zero delay buffer with output divider
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
■
Up to Three Clock Frequency Domains
■
Flexible Clock Reference and External
Feedback Inputs
• Programmable single-ended or differential input
reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
■
8MHz to 267MHz Input/Output Operation
■
Low Output to Output Skew (<100ps)
■
Low Jitter Peak-to-Peak (< 70 ps)
■
Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
- 40 to 70
Ω
in 5
Ω
increments
• Programmable slew rate
• Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■
All Inputs and Outputs are Hot Socket
Compliant
■
Full JTAG Boundary Scan Test In-System
Programming Support
■
Exceptional Power Supply Noise Immunity
■
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■
48-pin and 64-pin TQFP Packages
■
Applications
•
•
•
•
Circuit board common clock distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer
■
Fully Integrated High-Performance PLL
•
•
•
•
•
Programmable lock detect
Three “Power of 2” output dividers (5-bit)
Programmable on-chip loop filter
Compatible with spread spectrum clocks
Internal/external feedback
■
Precision Programmable Phase Adjustment
(Skew) Per Output
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
ispClock5300S Family Functional Diagram
LO CK
PLL _ BYPASS
REFA /
REFP
REFB /
REFN
+
OUTPUT
DIVIDERS
1
0
1
SKEW
CONTROL
OUTPUT
DRIVERS
OUTPUT 1
PHASE
FREQ.
DETECT
LOOP
FILTER
V0
5-Bit
VCO
0
V1
5-bit
REFSEL
V2
5-bit
OUTPUT
ROUTING
MATRIX
FBK
OUTPUT N
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
DS1010_01.4
Lattice Semiconductor
ispClock5300S Family Data Sheet
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E
2
CMOS
®
memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Device
ispClock5320S
ispClock5316S
ispClock5312S
ispClock5308S
ispClock5304S
Number of Programmable
Clock Inputs
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
Number of Programmable
Single-Ended Outputs
20
16
12
8
4
Figure 1. ispClock5304S Functional Block Diagram
LO CK
RESET
PLL _ BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
1
0
1
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
OUTPUT
DIVIDERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
BANK_1B
SKEW
CONTROL
OUTPUT
DRIVERS
+
PHASE
DETECT
LOOP
FILTER
V0
5-bit
VCO
0
V1
5-bit
REFSEL
V2
5-bit
FBK
VTT_FBK
JTAG INTERFACE
TDI
TMS
TCK
TDO
2
Lattice Semiconductor
Figure 2. ispClock5308S Functional Block Diagram
LO CK
RESET
PLL _ BYPASS
OEX
ispClock5300S Family Data Sheet
OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
1
0
1
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
OUTPUT
DIVIDERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
V1
5-bit
+
PHASE
DETECT
LOOP
FILTER
V0
5-bit
VCO
0
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
REFSEL
V2
5-bit
FBK
VTT_FBK
SKEW
CONTROL
OUTPUT
DRIVERS
JTAG INTERFACE
TDI
TMS
TCK
TDO
Figure 3. ispClock5312S Functional Block Diagram
LO CK
RESET
PLL _ BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
1
0
1
LOCK
DETECT
+
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
OUTPUT
DIVIDERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
V1
5-bit
PHASE
DETECT
LOOP
FILTER
V0
5-bit
VCO
0
BANK_1B
BANK_2A
BANK_2B
REFSEL
V2
5-bit
FBK
VTT_FBK
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
JTAG INTERFACE
SKEW
CONTROL
OUTPUT
DRIVERS
TDI
TMS
TCK
TDO
3
Lattice Semiconductor
Figure 4. ispClock5316S Functional Block Diagram
LO CK
RESET
PLL _ BYPASS
OEX
ispClock5300S Family Data Sheet
OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
1
0
1
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
OUTPUT
DIVIDERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK _0 A
BANK _0 B
BANK _1 A
V1
5-bit
PHASE
DETECT
LOOP
FILTER
V0
5-bit
VCO
0
BANK _1 B
BANK _2 A
BANK _2 B
BANK _3 A
REFSEL
V2
5-bit
FBK
VTT_FBK
BANK _3 B
BANK _4 A
BANK _4 B
BANK _5 A
BANK _5 B
BANK _6 A
BANK _6 B
BANK _7 A
JTAG INTERFACE
SKEW
CONTROL
TDI
TMS
TCK
TDO
OUTPUT
DRIVERS
BANK _7 B
Figure 5. ispClock5320S Functional Block Diagram
LO CK
RESET
PLL _ BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
1
0
1
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
OUTPUT
DIVIDERS
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_0A
BANK_0B
BANK_1A
V1
5-bit
PHASE
DETECT
LOOP
FILTER
V0
5-bit
VCO
0
BANK_1B
BANK_2A
BANK_2B
BANK_3A
REFSEL
V2
5-bit
FBK
VTT_FBK
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
JTAG INTERFACE
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_9B
TDI
TMS
TCK
TDO
4
Lattice Semiconductor
ispClock5300S Family Data Sheet
Absolute Maximum Ratings
ispClock5300S
Core Supply Voltage V
CCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage V
CCA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage V
CCJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage V
CCO
. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
ispClock5300S
Symbol
V
CCD
V
CCJ
V
CCA
V
CCXSLEW
T
JOP
T
A
Parameter
Core Supply Voltage
JTAG I/O Supply Voltage
Analog Supply Voltage
V
CC
Turn-on Ramp Rate
Operating Junction Temperature
Ambient Operating Temperature
All supply pins
Commercial
Industrial
Commercial
Industrial
Conditions
Min.
3.0
1.62
3.0
—
0
-40
0
-40
Max.
3.6
3.6
3.6
0.33
120
130
70
1
85
1
Units
V
V
V
V/µs
°C
°C
1. Device power dissipation may also limit maximum ambient operating temperature.
Recommended Operating Conditions – V
CCO
vs. Logic Standard
V
CCO
(V)
Logic Standard
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL1.8
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
eHSTL Class 1
Min.
3.0
1.71
2.375
3.0
1.71
2.375
3.0
1.425
1.71
Typ.
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.5
1.8
Max.
3.6
1.89
2.625
3.6
1.89
2.625
3.6
1.575
1.89
Min.
—
—
—
—
0.84
1.15
1.30
0.68
0.84
V
REF
(V)
Typ.
—
—
—
—
0.90
1.25
1.50
0.75
0.90
Max.
—
—
—
—
0.95
1.35
1.70
0.90
0.95
Min.
—
—
—
—
—
V
REF
- 0.04
V
REF
- 0.05
—
—
V
TT
(V)
Typ.
—
—
—
—
0.5 x V
CCO
V
REF
V
REF
0.5 x V
CCO
0.5 x V
CCO
Max.
—
—
—
—
—
V
REF
+ 0.04
V
REF
+ 0.05
—
—
Note: ‘—’ denotes V
REF
or V
TT
not applicable to this logic standard
5
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