Changes to Ordering Guide .......................................................... 30
6/2010—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
SPECIFICATIONS
ADP2140
V
IN1
= 3.6 V, V
IN2
= V
OUT2
+ 0.3 V or 1.65 V, whichever is greater; 5 V EN1 = EN2 = V
IN1
; I
OUT
= 200 mA, I
OUT2
= 10 mA, C
IN
= 10 μF,
C
OUT
= 10 µF, C
OUT2
= 1 µF, L
OUT
= 1 μH; T
J
= −40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for typical
specifications, unless otherwise noted.
Table 1.
Parameter
BUCK SECTION
Input Voltage Range
Buck Output Accuracy
Symbol
V
IN1
V
OUT
Test Conditions/Comments
Min
2.3
−1.5
−2.5
Typ
Max
5.5
+1.5
+2.5
Unit
V
%
%
Transient Load Regulation
V
TR-LOAD
Transient Line Regulation
V
TR-LINE
PWM To PSM Threshold
Output Current
Current Limit
Switch On Resistance
PFET
NFET
Switch Leakage Current
Quiescent Current
Minimum On Time
Oscillator Frequency
Frequency Foldback Threshold
Start-Up Time
1
Soft Start Time
2
LDO SECTION
Input Voltage Range
LDO Output Accuracy
I
OUT
= 10 mA
V
IN1
= 2.3 V or (V
OUT
+ 0.5 V) to 5.5 V, I
OUT
= 1 mA to
600 mA
V
OUT
= 1.8 V
Load = 50 mA to 250 mA, rise/fall time = 200 ns
Load = 200 mA to 600 mA, rise/fall time = 200 ns
Line transient = 4 V to 5 V, 4 μs rise time
V
OUT
= 1.0 V
V
OUT
= 1.8 V
V
OUT
= 3.3 V
V
IN1
= 2.3 V or (V
OUT
+ 0.5 V) to 5.5 V
V
IN1
= 2.3 V or (V
OUT
+ 0.5 V) to 5.5 V
V
IN1
= 2.3 V to 5.5 V
V
IN1
= 2.3 V to 5.5 V
EN1 = GND, VIN1 = 5.5 V, and SW = 0 V
No load, device not switching
75
75
40
25
25
100
1100
250
250
20
70
3.0
50
70
150
−1
30
3.15
600
1300
mV
mV
mV
mV
mV
mA
mA
mA
mΩ
mΩ
μA
μA
ns
MHz
%
µs
μs
V
%
%
%
%/V
%/mA
mV
mV
μA
μA
μA
dB
dB
dB
dB
I
OUT
I
LIM
R
PFET
R
NFET
I
LEAK-SW
I
Q
ON-TIME
MIN
FREQ
V
FOLD
t
START-UP
SS
TIME
V
IN2
V
OUT2
2.55
Output voltage where f
SW
≤ 50% of nominal frequency
V
OUT
= 1.8 V, 600 mA load
V
OUT
= 1.8 V, 600 mA load
1.65
−1
−1.5
−3
−0.05
Line Regulation
Load Regulation
3
Dropout Voltage
4
Ground Current
∆V
OUT2
/∆V
IN2
∆V
OUT2
/∆I
OUT2
V
DROPOUT
I
AGND
Power Supply Rejection Ratio
PSRR on V
IN2
PSRR
I
OUT2
= 10 mA, T
J
= 25°C
1 mA < I
OUT2
< 300 mA, V
IN2
= (V
OUT2
+ 0.3 V) to 5.5 V, T
J
= 25°C
1 mA < I
OUT2
< 300 mA, V
IN2
= (V
OUT2
+ 0.3 V) to 5.5 V
V
IN2
= (V
OUT2
+ 0.3 V) to 5.5 V, I
OUT2
= 10 mA
I
OUT2
= 1 mA to 300 mA
I
OUT2
= 10 mA, V
OUT2
= 1.8 V
I
OUT2
= 300 mA, V
OUT2
= 1.8 V
No load, buck disabled
I
OUT2
= 10 mA
I
OUT2
= 300 mA
V
IN2
= V
OUT2
+ 1 V, V
IN1
= 5 V, I
OUT2
= 10 mA
10 kHz, V
OUT2
= 1.2 V, 1.8 V, 3.3 V
100 kHz, V
OUT2
= 3.3 V
100 kHz, V
OUT2
= 1.8 V
100 kHz, V
OUT2
= 1.2 V
5.5
+1
+1.5
+3
+0.05
0.005
7
200
35
90
220
0.001
4
110
22
65
150
65
53
54
55
Rev. B | Page 3 of 32
ADP2140
Parameter
Output Noise
Symbol
OUT
NOISE
Test Conditions/Comments
V
IN2
= V
IN1
= 5 V, I
OUT2
= 10 mA
10 Hz to 100 kHz, V
OUT2
= 0.8 V
10 Hz to 100 kHz, V
OUT2
= 1.2 V
10 Hz to 100 kHz, V
OUT2
= 1.8 V
10 Hz to 100 kHz, V
OUT2
= 2.5 V
10 Hz to 100 kHz, V
OUT2
= 3.3 V
T
J
= 25°C
EN2 = GND, V
IN2
= 5.5 V and V
OUT2
= 0 V
V
OUT2
= 3.3 V, 300 mA load
V
OUT2
= 3.3 V, 300 mA load
Min
Typ
29
40
50
66
88
500
70
130
Data Sheet
Max
Unit
µV rms
µV rms
µV rms
µV rms
µV rms
mA
μA
µs
μs
Current Limit
Input Leakage Current
Start-Up Time
1
Soft Start Time
2
ADDITIONAL FUNCTIONS
Undervoltage Lockout
Input Voltage Rising
Input Voltage Falling
EN Input
EN1, EN2 Input Logic High
EN1, EN2 Input Logic Low
EN1, EN2 Input Leakage
Shutdown Current
Thermal Shutdown
Threshold
Hysteresis
Power Good
Rising Threshold
Falling Threshold
Power-Good Hysteresis
Output Low
Leakage Current
Buck to LDO Delay
Power-Good Delay
1
2
I
LIM
I
LEAK-LDO
t
START-UP
SS
TIME
UVLO
UVLO
RISE
UVLO
FALL
V
IH
V
IL
I
EN-LKG
I
SHUT
TS
SD
TS
SD-HYS
PG
RISE
PG
FALL
PG
HYS
V
OL
I
OH
t
DELAY
t
RESET
360
760
1
2.05
2.3 V ≤ V
IN1
≤ 5.5 V
2.3 V ≤ V
IN1
≤ 5.5 V
EN1, EN2 = V
IN1
or GND
EN1, EN2 = V
IN1
or GND
V
IN1
= 5.5 V, EN1, EN2 = GND, T
J
= −40°C to +85°C
T
J
rising
1.0
2.23
2.16
2.3
V
V
V
V
µA
µA
μA
°C
°C
%V
OUT
%V
OUT
%V
OUT
V
μA
ms
ms
0.27
0.05
0.3
150
20
92
86
6
1
1.2
I
SINK
= 4 mA
Power-good pin pull-up voltage = 5.5 V
PWM mode only
PWM mode only
0.2
1
5
5
Start-up time is defined as the time between the rising edge of ENx to V
OUTx
being at 10% of the V
OUTx
nominal value.
Soft start time is defined as the time between V
OUTx
being at 10% to V
OUTx
being at 90% of the V
OUTx
nominal value.
3
Based on an endpoint calculation using 1 mA and 300 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE
1
Buck
LDO
CAPACITOR ESR
Buck
LDO
MINIMUM INDUCTOR
1
Symbol
C
MIN
C
MIN
Test Conditions/Comments
T
A
= −40°C to +125°C
Min
7.5
0.7
Typ
10
1.0
Max
Unit
µF
µF
Ω
Ω
Ω
μH
T
A
= −40°C to +125°C
R
ESR
R
ESR
IND
MIN
0.001
0.001
0.7
0.01
1
1
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 32
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN1, VIN2 to PGND, AGND
VOUT2 to PGND, AGND
SW to PGND, AGND
FB to PGND, AGND
PG to PGND, AGND
EN1, EN2 to PGND, AGND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to V
IN2
−0.3 V to V
IN1
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
ADP2140
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a 4-layer, 4 in. × 3 in. circuit
board. Refer to JESD 51-7 for detailed information on the board
construction.
For more information, see
AN-772
Application Note,
A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12,
Guidelines for
Reporting and Using Package Thermal Information,
states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
JB
measures the component power flowing through
multiple thermal paths rather than a single path, as in thermal
resistance, θ
JB
. Therefore, Ψ
JB
thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make Ψ
JB
more useful in real-world applications.
Maximum junction temperature (T
J
) is calculated from the
board temperature (T
B
) and power dissipation (P
D
) using the
formula
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ
JB
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in com-
bination. The ADP2140 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (T
J
) of the device is dependent on the
ambient temperature (T
A
), the power dissipation of the device
(P
D
), and the junction-to-ambient thermal resistance of the
package (θ
JA
).
Maximum junction temperature (T
J
) is calculated from the
ambient temperature (T
A
) and power dissipation (P
D
) using the
formula
T
J
=
T
A
+ (P
D
×
θ
JA
)
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
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