BF1205C
Dual N-channel dual gate MOS-FET
Rev. 3 — 7 September 2011
Product data sheet
1. Product profile
1.1 General description
The BF1205C is a combination of two dual gate MOS-FET amplifiers with shared source
and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1
bias of amplifier b.
The source and substrate are interconnected. Internal bias circuits enable DC stabilization
and a very good cross-modulation performance during AGC. Integrated diodes between
the gates and source protect against excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features and benefits
Two low noise gain controlled amplifiers in a single package; one with a fully integrated
bias and one with a partly integrated bias
Internal switch to save external components
Superior cross-modulation performance during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance ratio.
1.3 Applications
Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply
voltage
digital and analog television tuners
professional communication equipment.
NXP Semiconductors
BF1205C
Dual N-channel dual gate MOS-FET
1.4 Quick reference data
Table 1.
Quick reference data
Per MOS-FET unless otherwise specified.
Symbol Parameter
V
DS
I
D
P
tot
y
fs
drain-source voltage
drain current (DC)
total power dissipation
forward transfer admittance
T
sp
107
C
f = 1 MHz
amplifier a; I
D
= 19 mA
amplifier b; I
D
= 13 mA
C
ig1-ss
input capacitance at gate 1
f = 1 MHz
amplifier a
amplifier b
C
rss
NF
X
mod
reverse transfer capacitance f = 1 MHz
noise figure
cross-modulation
amplifier a; f = 400 MHz
amplifier b; f = 800 MHz
input level for k = 1 % at
40 dB AGC
amplifier a
amplifier b
T
j
[1]
[1]
Conditions
Min
-
-
-
26
28
-
-
-
-
-
Typ
-
-
-
31
33
2.2
2.0
20
1.3
1.4
Max Unit
6
30
180
41
43
2.7
2.5
-
1.9
2.1
V
mA
mW
mS
mS
pF
pF
fF
dB
dB
100
100
-
105
103
-
-
-
150
dBV
dBV
C
junction temperature
T
sp
is the temperature at the soldering point of the source lead.
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
Discrete pinning
Description
gate 1 (a)
gate 2
gate 1 (b)
drain (b)
source
drain (a)
1
2
3
G2
S
6
5
4
G1
(A)
AMP a
D
(A)
Simplified outline
Symbol
001aaa706
G1
(B)
AMP b
sym033
D
(B)
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
2 of 23
NXP Semiconductors
BF1205C
Dual N-channel dual gate MOS-FET
3. Ordering information
Table 3.
Ordering information
Package
Name
BF1205C
-
Description
plastic surface mounted package; 6 leads
Version
SOT363
Type number
4. Marking
Table 4.
BF1205C
[1]
* = p or -: made in Hong Kong.
* = t: made in Malaysia.
* = W: made in China.
Marking
Marking code
[1]
M6*
Type number
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
[1]
Parameter
drain-source voltage
drain current (DC)
gate 1 current
gate 2 current
total power dissipation
storage temperature
junction temperature
Conditions
Min
-
-
-
-
Max
6
30
10
10
180
+150
150
Unit
V
mA
mA
mA
mW
C
C
Per MOS-FET
T
sp
107
C
[1]
-
65
-
T
sp
is the temperature at the soldering point of the source lead.
6. Thermal characteristics
Table 6.
Symbol
R
th(j-s)
Thermal characteristics
Parameter
thermal resistance from junction
to soldering point
Conditions
Typ
240
Unit
K/W
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
3 of 23
NXP Semiconductors
BF1205C
Dual N-channel dual gate MOS-FET
250
P
tot
(mW)
200
001aac193
150
100
50
0
0
50
100
150
T
sp
(˚C)
200
Fig 1.
Power derating curve.
7. Static characteristics
Table 7.
Static characteristics
T
j
= 25
C.
Symbol
V
(BR)DSS
Parameter
drain-source breakdown voltage
Conditions
V
G1-S
= V
G2-S
= 0 V; I
D
= 10
A
amplifier a
amplifier b
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
V
GS
= V
DS
= 0 V; I
G1-S
= 10 mA
V
GS
= V
DS
= 0 V; I
G2-S
= 10 mA
V
G2-S
= V
DS
= 0 V; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0 V; I
S-G2
= 10 mA
V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 100
A
V
DS
= 5 V; V
G1-S
= 5 V; I
D
= 100
A
V
G2-S
= 4 V; V
DS(b)
= 5 V; R
G1
= 150 k
amplifier a; V
DS(a)
= 5 V
amplifier b
I
G1-S
gate 1 cut-off current
V
G2-S
= V
DS(a)
= 0 V
amplifier a; V
G1-S(a)
= 5 V; I
D(b)
= 0 A
amplifier b; V
G1-S(b)
= 5 V; V
DS(b)
= 0 V
I
G2-S
gate 2 cut-off current
V
G2-S
= 4 V;
V
G1-S(a)
= V
DS(a)
= V
DS(b)
= 0 V;
V
G1-S(b)
= 0 V;
-
-
-
-
-
-
50
50
20
nA
nA
nA
[1]
[2]
Min
Typ
Max Unit
Per MOS-FET; unless otherwise specified
6
6
6
6
0.5
0.5
0.3
0.4
14
9
-
-
-
-
-
-
-
-
-
-
-
-
10
10
1.5
1.5
1.0
1.0
24
17
V
V
V
V
V
V
V
V
mA
mA
[1]
[2]
R
G1
connects gate 1 (b) to V
GG
= 0 V (see
Figure 3).
R
G1
connects gate 1 (b) to V
GG
= 5 V (see
Figure 3).
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
4 of 23
NXP Semiconductors
BF1205C
Dual N-channel dual gate MOS-FET
20
I
D
(mA)
16
001aaa552
(1)
12
(2)
(3)
G1 (A)
D (A)
8
(4)
G2
S
4
(6)
(5)
G1 (B)
RG1
D (B)
0
0
1
2
3
4
V
GG
(V)
5
V
GG
001aaa553
(1) I
D(b)
; R
G1
= 120 k.
(2) I
D(b)
; R
G1
= 150 k.
(3) I
D(b)
; R
G1
= 180 k.
(4) I
D(a)
; R
G1
= 180 k.
(5) I
D(a)
; R
G1
= 150 k.
(6) I
D(a)
; R
G1
= 120 k.
V
GG
= 5 V: amplifier a is off; amplifier b is on
V
GG
= 0 V: amplifier a is on; amplifier b is off.
Fig 2.
Drain currents of MOS-FET a and b as function
of V
GG
.
Fig 3.
Functional diagram.
8. Dynamic characteristics
8.1 Dynamic characteristics for amplifier a
Table 8.
Dynamic characteristics for amplifier a
[1]
Common source; T
amb
= 25
C; V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 19 mA.
Symbol
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
G
tr
Parameter
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
reverse transfer capacitance
power gain
Conditions
T
j
= 25
C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
B
S
= B
S(opt)
; B
L
= B
L(opt)
f = 200 MHz; G
S
= 2 mS; G
L
= 0.5 mS
f = 400 MHz; G
S
= 2 mS; G
L
= 1 mS
f = 800 MHz; G
S
= 3.3 mS; G
L
= 1 mS
NF
noise figure
f = 11 MHz; G
S
= 20 mS; B
S
= 0 S
f = 400 MHz; Y
S
= Y
S(opt)
f = 800 MHz; Y
S
= Y
S(opt)
31
26
21
-
-
-
35
30
25
3.0
1.3
1.4
39
34
29
-
1.9
2.1
dB
dB
dB
dB
dB
dB
Min
26
-
-
-
-
Typ Max
31
2.2
3.0
0.9
20
41
2.7
-
-
-
Unit
mS
pF
pF
pF
fF
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
5 of 23
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