FAN5078 DDR/ACPI Regulator Combo
May 2006
FAN5078
DDR/ACPI Regulator Combo
Features
PWM regulator for VDDQ (2.5V or 1.8)
Linear LDO regulator generates VTT = VDDQ/2,
1.5A Peak sink/source capability
AMT / M-state support
Control to generate 5V USB
ACPI drive and control for 5V DUAL generation
3.3V internal LDO for 3V-ALW generation
300 kHz fixed frequency switching
R
DS(ON)
current sensing or optional current sense resistor
for precision over-current detect
Internal synchronous boot diode
Common Power Good signal for all voltages
Input under-voltage lockout (UVLO)
Thermal shutdown
Latched multi-fault protection
Precision reference output for ULDO controllers
24-pin 5 x 5 MLP package
Description
The FAN5078 DDR memory regulator combines a high-
efficiency Pulse-Width Modulated (PWM) controller to
generate the memory supply voltage, VDDQ, and a linear
regulator to generate termination voltage (VTT).
Synchronous rectification provides high efficiency over a wide
range of load currents. Efficiency is further enhanced by using
the low-side MOSFET’s R
DS(ON)
to sense current.
The VDDQ PWM regulator is a sampled current mode control
with external compensation to achieve fast load-transient
response and provide system design optimization.
The VTT regulator derives its reference and takes its power
from the VDDQ PWM regulator, output. The VTT termination
regulator is capable of sourcing or sinking 1.5A peak currents.
In S5 M1 mode, the VDDQ switcher, VTT regulator, and the
3.3V regulators remain on. S3 mode keeps these regulators
on, but also turns on an external P-Channel to provide 5V
USB.
A single soft-start capacitor enables controlled slew rates for
both VDDQ and 3.3V-ALW outputs.
PGOOD becomes true in S0 only after all regulators have
achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on while the other
regulators are powered down.
Applications
DDR VDDQ and VTT voltage generation with ACPI
support
Desktop PC's
Servers
Ordering Information
Part Number
FAN5078MPX
Temperature Range
-10°C to 85°C
Package
MLP-24 5x5mm
Packing
Tape and Reel
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/09/06
www.fairchildsemi.com
FAN5078 DDR/ACPI Regulator Combo
Block Diagrams
R4
+5VSB
+12V
+5MAIN
S3#O
Q4
C13
Q7
+5VSB
SBSW
Q6
+5MAIN
S3#O
3
1
16
18
17
15
13
9
10
C3
SS
VCC
21
14
11
HDRV
SW
ISNS
R3
Q2
LDRV
GND
FB
C9
COMP
VDDQ IN
REF IN
VTT SNS
VTT OUT
C7
C8
R10
Q3
5V USB
C14
C15
SBUSB#
3.3 MAIN
Q5
4
5V MAIN
S4ST#
BOOT
Q1
C5
C2
5V DUAL
L2
S3#O
EN
S3#I
3.3 ALW
PGOOD
ACPI
CONTROL
&
LOGIC
2
8
C
IN
C12
L1
VDDQ
C
OUT
+5VSB
PWM
C4
R5
ILIM
12
P1
23
22
7
R2
R1
R6
C6
R9
20
VTT
LDO
24
5
6
Figure 1. Typical DDR/ACPI System Regulation Schematic
Components are selected for a 15A VDDQ output.
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
2
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FAN5078 DDR/ACPI Regulator Combo
Table 1. BOM for Figure 1
Ref.
Q1
Q2
Q3
Q4, Q6
Q5
Q7
C12,C15
C13
C14
C2
C4, C8
C3, C5
C6
C7
C9
CIN
COUT
L1
L2
R1,R2,R3,R9,R10
R4
R5
R6
Qty Description
1
1
1
2
1
1
2
1
1
1
2
2
1
1
1
4
3
1
1
5
1
1
1
NFET, 30V, 50A, 9mΩ, DPAK
NFET, 30V, 85A, 5mΩ, DPAK
NFET, 30V, 58A, 11mΩ, DPAK
PFET, 20V, 5.5A, 30mΩ, SSOT6
NFET, 20V, 6.2A, 20mΩ, SSOT6
NFET, 30V, 30A, 22mΩ, DPAK
330uf, 10V, 20%, 110mΩ
10nf, 50V, 10%, X7R
3.3nf, 50V, 10%, X7R
4.7uf, 25V, 20%, X5R
1.0uf, 10V, 10%, X5R
0.1uf, 16V, 10%, X7R
4.7nf, 50V, 10%, X7R
820uf, 6.3V, 20%, 36mΩ
82pf, 50V, 5%, NPO
1200uf, 6.3V, 20%, 18mΩ
1200uf, 6.3V, 20%, 18mΩ
IND, 1.8uH, 16A, 3.2mΩ
IND, 470nH, 16A, 2.6mΩ
1.21K, 1%
3.9K, 5%
71.5K, 1%
15.0K, 1%
Inter-Technical SC5018-1R8M
Inter-Technical SC2511-R47M
Mfg. and Part Number
Fairchild FDD6296
Fairchild FDD8896
Fairchild FDD8880
Fairchild FDC602P
Fairchild FDC637AN
Fairchild FDD6612A
Contact a Fairchild representative for complete reference design and / or evaluation board.
Bypass Capacitor Notes:
1. Input capacitor C
IN
is typically chosen based on the ripple current requirements. C
OUT
is typically selected based on both
current ripple rating and ESR requirement. See AN-6006 for these calculations.
2. C7, C12, and C15 selection is largely determined by ESR and load transient response requirements. In each case, the
number of capacitors required depends on the capacitor technology chosen. Oscons can meet the requirements with less
space, but higher cost, than using low-ESR electrolytics.
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
3
www.fairchildsemi.com
FAN5078 DDR/ACPI Regulator Combo
5VSB
VCC
D2
BOOT
C
BOOT
VIN
Q1
S3#I
S3
HDRV
OVP
FB
RAMP
CLK
COMP
FB
S
Q
R
RAMP
S/H
SW
Q2
VDD
LDRV
PGND
L
OUT
VDDQ
C
OUT
EN
POR/UVLO
ADAPTIVE
GATE
CONTROL LOGIC
PWM
OSC
PWM
4.41K
ILIM det.
ISNS
SS
PGOOD
VDDQ IN
ISNS
R
SENSE
CURRENT PROCESSING
Reference and
Soft Start
VREF
ILIM
R
ILIM
VDDQ
Figure 2. PWM Modulator Block Diagram
VDDQ IN
R9
S3#I
50K
REF IN
R10
VDDQ IN
+
50K
EN
VTT OUT
–
110K
VTT SNS
PGND
Figure 3. VTT Regulator Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
4
www.fairchildsemi.com
FAN5078 DDR/ACPI Regulator Combo
Pin Configuration
REF IN
COMP
GND
19
24
23
22
21
ILIM
20
SS
FB
SBUSB#
S4ST#
SBSW
5V MAIN
VTT SNS
VTT OUT
EN
S3#I
S3#O
3.3 ALW
VCC
PGOOD
18
VDDQ IN
SW
HDRV
ISNS
FAN5078MP 5x5mm MLP package (
θ
JA
= 38°C/W)
Note: Connect P1 pad to GND.
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin
SBUSB#
S4ST#
SBSW
5V MAIN
VTT SNS
VTT OUT
VDDQ IN
BOOT
HDRV
SW
ISNS
LDRV
PGOOD
Pin Function Description
USB Standby.
Pulls low with constant current to limit slew rate in S3 if S4ST# is high. Drives a P-
Channel MOSFET to connect 5VSB to 5V USB.
S4_STATE#
Connect to system logic signal that enables 5V USB power in S3.
Standby Switch.
Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in S3. High in
S0 and S5.
5V MAIN.
When this pin is below 4.5V, transition from S3 to S0 is inhibited.
VTT
remote sense input.
VTT
regulator power output.
VDDQ Input
from PWM. Connect to VDDQ output voltage. This is the VTT Regulator power input.
Boot.
Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot
diode to VCC.
High-Side Drive.
High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.
Switching Node.
Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and low-side MOSFET drain.
Current Sense Input.
Monitors the voltage drop across the lower MOSFET or external sense resistor
for current feedback and current limiting.
Low-Side Drive
The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.
Power Good Flag.
An open-drain output that pulls LOW when FB is outside of a ±10% range of the
0.9V reference or the VTT output is < 80% or > 110% of its reference. PGOOD goes low when the IC
is in the S5 state. The power-good signal from the PWM regulator enables the VTT regulator.
VCC.
Provides IC bias and gate drive power. The IC is held in standby until this pin is above the UVLO
threshold.
5
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14
VCC
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
BOOT
LDRV
1
2
3
17
16
P1 = GND
15
4
5
6
7
8
9
10
11
12
14
13
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