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PCKEL14D-T

Description
Clock Drivers u0026 Distribution 2.5/3.3V PECL/ECL 1:5 CLK DRVR
Categorysemiconductor    Analog mixed-signal IC   
File Size89KB,16 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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PCKEL14D-T Overview

Clock Drivers u0026 Distribution 2.5/3.3V PECL/ECL 1:5 CLK DRVR

PCKEL14D-T Parametric

Parameter NameAttribute value
Product CategoryClock Drivers & Distribution
ManufacturerNXP
RoHSDetails
Mounting StyleSMD/SMT
Package / CaseSOT-163
PackagingCut Tape
PackagingReel
Factory Pack Quantity2000
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Rev. 01 — 14 October 2002
Product data
1. Description
The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low
skew clock distribution applications. The device can be driven by either a differential
or single-ended ECL, or if positive power supplies are used, PECL input signal. The
PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of
−2.375
V to
−3.8
V (or 2.375 V to 3.8 V).
The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower
speed scan or test clock along with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor), the SEL pin will select the
differential clock input.
The common enable (EN) is synchronous, so that the outputs will only be
enabled/disabled when they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled, as can happen
with an asynchronous control. The internal flip-flop is clocked on the falling edge of
the input clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The V
BB
pin (an internally generated voltage supply) is available to this device only.
For single-ended conditions, the unused differential input is connected to V
BB
as a
switching reference voltage. V
BB
may also rebias AC-coupled inputs. When used,
decouple V
BB
and V
CC
via a 0.01
µF
capacitor and limit current sourcing or sinking to
0.1 mA. When not used, V
BB
should be left open.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
50 ps output-to-output skew at 3.3 V
Synchronous enable/disable
Multiplexed clock input
ESD protection: > 2.5 kV HBM
The PCK series contains temperature compensation
PECL mode operating range: V
CC
= 2.375 V to 3.8 V, with V
EE
= 0 V
NECL mode operating range: V
CC
= 0 V, with V
EE
=
−2.375
V to
−3.8
V
Internal 75 kΩ pull-down resistors on all inputs, plus a 37.5 kΩ pull-up on CLK
Q output will default LOW with inputs open or at V
EE
Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test
Moisture sensitivity level 1
Flammability rating: UL-94 code V-0 @ 1/8”

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