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EP3SL70F780C4N

Description
FPGA - Field Programmable Gate Array FPGA - Stratix III 2700 LABs 488 IOs
CategoryProgrammable logic devices    Programmable logic   
File Size191KB,16 Pages
ManufacturerAltera (Intel)
Environmental Compliance
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EP3SL70F780C4N Overview

FPGA - Field Programmable Gate Array FPGA - Stratix III 2700 LABs 488 IOs

EP3SL70F780C4N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerAltera (Intel)
Parts packaging codeBGA
package instructionBGA, BGA780,28X28,40
Contacts780
Reach Compliance Codecompliant
ECCN code3A991
Other featuresIT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY
maximum clock frequency717 MHz
JESD-30 codeS-PBGA-B780
JESD-609 codee1
length29 mm
Humidity sensitivity level3
Number of entries488
Number of logical units67500
Output times488
Number of terminals780
Maximum operating temperature85 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA780,28X28,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)245
power supply1.2/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage0.94 V
Minimum supply voltage0.86 V
Nominal supply voltage0.9 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width29 mm
1. Stratix III Device Family Overview
SIII51001-1.8
The Stratix
®
III family provides one of the most architecturally advanced,
high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative
Programmable Power Technology, which provides the ability to turn on the
performance where needed and turn down the power consumption for blocks not in
use. Selectable Core Voltage and the latest in silicon process optimizations are also
employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III
FPGA family offers two variants optimized to meet different application needs:
The Stratix III
L
family provides balanced logic, memory, and multiplier ratios for
mainstream applications.
The Stratix III
E
family is memory- and multiplier-rich for data-centric
applications.
Modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high-speed I/O. Package and die enhancements with
dynamic on-chip termination, output delay, and current strength control provide
best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a
programmable alternative to custom ASICs and programmable processors for
high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where
ultra-high reliability is required, Stratix III devices include automatic error detection
circuitry to detect data corruption by soft errors in the configuration random-access
memory (CRAM) and user memory cells.
Features Summary
Stratix III devices offer the following features:
48,000 to 338,000 equivalent logic elements (LEs) ( refer to
Table 1–1)
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM
block sizes to implement true dual-port memory and FIFO buffers
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,
and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for
robust signal integrity
Programmable Power Technology, which minimizes power while maximizing
device performance
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1
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