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MC10H107FN

Description
Logic Gates Triple 2-Input
Categorylogic    logic   
File Size143KB,6 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC10H107FN Overview

Logic Gates Triple 2-Input

MC10H107FN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeQLCC
package instructionPLASTIC, LCC-20
Contacts20
Reach Compliance Codenot_compliant
series10H
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.965 mm
Logic integrated circuit typeXOR/XNOR GATE
Humidity sensitivity level1
Number of functions3
Number of entries2
Number of terminals20
Maximum operating temperature75 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
method of packingRAIL
Peak Reflow Temperature (Celsius)240
Prop。Delay @ Nom-Sup1.7 ns
propagation delay (tpd)1.6 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width8.965 mm
MC10H107
Triple 2−Input Exclusive OR/
Exclusive NOR Gate
Description
The MC10H107 is a triple 2−input exclusive OR/NOR gate. This
MECL 10H™ part is a functional/pinout duplication of the standard
MECL 10K™ family part, with 100% improvement in propagation
delay, and no increase in power−supply current.
Features
http://onsemi.com
MARKING DIAGRAMS*
16
MC10H107L
AWLYYWW
CDIP−16
L SUFFIX
CASE 620A
1
Propagation Delay, 1.0 ns Typical
Power Dissipation 35 mW/Gate Typical (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K Compatible
Pb−Free Packages are Available*
16
16
1
PDIP−16
P SUFFIX
CASE 648
1
MC10H107P
AWLYYWWG
10H107
ALYWG
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H107G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
February, 2006
Rev. 7
1
Publication Order Number:
MC10H107/D

MC10H107FN Related Products

MC10H107FN MC10H107L
Description Logic Gates Triple 2-Input Logic Gates Triple 2-Input
Is it Rohs certified? incompatible incompatible
Maker ON Semiconductor ON Semiconductor
Parts packaging code QLCC DIP
package instruction PLASTIC, LCC-20 CERAMIC, DIP-16
Contacts 20 16
Reach Compliance Code not_compliant not_compliant
series 10H 10H
JESD-30 code S-PQCC-J20 R-GDIP-T16
JESD-609 code e0 e0
length 8.965 mm 19.49 mm
Logic integrated circuit type XOR/XNOR GATE XOR/XNOR GATE
Number of functions 3 3
Number of entries 2 2
Number of terminals 20 16
Maximum operating temperature 75 °C 75 °C
Package body material PLASTIC/EPOXY CERAMIC, GLASS-SEALED
encapsulated code QCCJ DIP
Encapsulate equivalent code LDCC20,.4SQ DIP16,.3
Package shape SQUARE RECTANGULAR
Package form CHIP CARRIER IN-LINE
method of packing RAIL RAIL
Peak Reflow Temperature (Celsius) 240 235
Prop。Delay @ Nom-Sup 1.7 ns 1.7 ns
propagation delay (tpd) 1.6 ns 1.6 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 4.57 mm 5.08 mm
surface mount YES NO
technology ECL ECL
Temperature level COMMERCIAL EXTENDED COMMERCIAL EXTENDED
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form J BEND THROUGH-HOLE
Terminal pitch 1.27 mm 2.54 mm
Terminal location QUAD DUAL
Maximum time at peak reflow temperature 30 NOT SPECIFIED
width 8.965 mm 7.62 mm
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