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74LVC16374ADL-T

Description
Flip Flops 3.3V 16-BIT POS D-TYPE 3-S
Categorylogic    logic   
File Size733KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74LVC16374ADL-T Overview

Flip Flops 3.3V 16-BIT POS D-TYPE 3-S

74LVC16374ADL-T Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSSOP
package instructionSSOP, SSOP48,.4
Contacts48
Reach Compliance Codeunknown
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G48
JESD-609 codee4
length15.875 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
Maximum Frequency@Nom-Sup100000000 Hz
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits8
Number of functions2
Number of ports2
Number of terminals48
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP48,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup7 ns
propagation delay (tpd)7.5 ns
Certification statusNot Qualified
Maximum seat height2.8 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width7.5 mm
Base Number Matches1
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 11 — 16 January 2013
Product data sheet
1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state
outputs for bus-oriented applications. It consists of two sections of eight positive
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for
each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and
5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C

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Description Flip Flops 3.3V 16-BIT POS D-TYPE 3-S Flip Flops 74LVCH16374ABQ/HUQFN60U/REEL13 Flip Flops 74LVC16374ADGG-Q100/TSSOP48/RE Flip Flops 3.3V 16-BIT POS Flip Flops 16-BIT 5V TOL. I/O Flip Flops 74LVC16374ABQ/HUQFN60U/REEL13D Flip Flops 16-BIT 5V TOL. I/O Flip Flops 16-BIT 5V TOL. I/O BUFFER D
Product Category - Flip Flops - Flip Flops Flip Flops Flip Flops Flip Flops -
Manufacturer - NXP - NXP NXP NXP NXP -

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