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AT91SAM7S256D-AU

Description
Supervisory Circuits Dual Switch Debouncer
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size4MB,776 Pages
ManufacturerAtmel (Microchip)
Environmental Compliance
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AT91SAM7S256D-AU Overview

Supervisory Circuits Dual Switch Debouncer

AT91SAM7S256D-AU Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerAtmel (Microchip)
package instructionLFQFP, QFP64,.47SQ,20
Reach Compliance Codecompliant
ECCN code3A991.A.2
Has ADCYES
Address bus width
bit size32
CPU seriesARM7
maximum clock frequency50 MHz
DAC channelNO
DMA channelYES
External data bus width
JESD-30 codeS-PQFP-G64
length10 mm
Humidity sensitivity level3
Number of I/O lines32
Number of terminals64
On-chip program ROM width32
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP64,.47SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
power supply1.8,3.3 V
Certification statusNot Qualified
RAM (bytes)65536
rom(word)65536
ROM programmabilityFLASH
Maximum seat height1.6 mm
speed55 MHz
Maximum supply voltage1.95 V
Minimum supply voltage1.65 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
width10 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
Base Number Matches1
AT91SAM
ARM-based Flash MCU
SAM7S512 SAM7S256 SAM7S128 SAM7S64
SAM7S321 SAM7S32 SAM7S161 SAM7S16
Features
Incorporates the ARM7TDMI
®
ARM
®
Thumb
®
Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
In-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash
– 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256
Bytes (Dual Plane)
– 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)
– 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)
– 16 Kbytes (SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash
Security Bit
– Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (SAM7S512/256)
– 32 Kbytes (SAM7S128)
– 16 Kbytes (SAM7S64)
– 8 Kbytes (SAM7S321/32)
– 4 Kbytes (SAM7S161/16)
Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
Reset Controller (RSTC)
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500
Hz) and Idle Mode
– Three Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) External Interrupt Source(s)
and One Fast Interrupt Source, Spurious Interrupt Protected
6175M–ATARM–26-Oct-12

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