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7024S55PF8

Description
SRAM 4KX16 DUAL PORT STAT RAM
Categorystorage   
File Size185KB,22 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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7024S55PF8 Overview

SRAM 4KX16 DUAL PORT STAT RAM

7024S55PF8 Parametric

Parameter NameAttribute value
Product CategorySRAM
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSNo
Memory Size64 kbit
Organization4 k x 16
Access Time55 ns
Interface TypeParallel
Supply Voltage - Max5.5 V
Supply Voltage - Min4.5 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTQFP-100
PackagingReel
Height1.4 mm
Length14 mm
Memory TypeSDR
Moisture SensitiveYes
Factory Pack Quantity750
TypeAsynchronous
Width14 mm
Unit Weight0.023175 oz
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
IDT7024S/L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts availble, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
11L
A
0L
(1,2)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
12
(1,2)
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
2740 drw 01
M/S
JUNE 2013
1
©2013 Integrated Device Technology, Inc.
DSC 2740/14
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