870919BRILF datasheet, PDF - EEWORLD Datasheet

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870919BRILF: DescriptionClock Generators u0026 Support Products 8-OUTPUT LVCMOS CLK GENERATOR; Categorysemiconductor Analog mixed-signal IC; File Size212KB，17 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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870919BRILF Overview

Clock Generators u0026 Support Products 8-OUTPUT LVCMOS CLK GENERATOR

870919BRILF Parametric

Parameter Name	Attribute value
Product Category	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)
RoHS	Details
Type	Clock Generators
Maximum Input Frequency	100 MHz
Max Output Freq	160 MHz
Number of Outputs	8 Output
Operating Supply Voltage	3.3 V
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Mounting Style	SMD/SMT
Package / Case	QSOP-28
Packaging	Tube
Height	1.47 mm
Jitter	165 ps
Length	9.9 mm
Factory Pack Quantity	48
Width	3.8 mm

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LVCMOS Clock Generator

ICS870919I

DATA SHEET

General Description

The ICS870919I is an LVCMOS clock generator that uses an internal

phase lock loop (PLL) for frequency multiplication and to lock the

low-skew outputs to the selected reference clock. The device offers

eight outputs. The PLL loop filter is completely internal and does not

require external components. Several output configurations of the

PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow

applications to optimize frequency generation over a wide range of

input reference frequencies. The PLL can also be disabled by the

PLL_EN control signal to allow for low frequency or DC testing. The

LOCK output asserts to indicate when phase-lock has been

achieved. The ICS870919I device is a member of the family of high

performance clock solutions from IDT.

Features

•

Two selectable single-ended input reference clocks

Eight single-ended clock outputs

Internal PLL does not require external loop filter components

5V tolerant inputs

Maximum output frequency: 160MHz, (2XQ output)

Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)

LVCMOS interface levels for all inputs and outputs

PLL disable feature for low-frequency testing

PLL lock output

Selectable synchronization of output to input edge

Output drive capability: ±24mA

Output skew: 300ps (maximum), Q0:Q4

Output skew: 500ps (maximum), all outputs

Full 3.3V supply voltage

Available in lead-free (RoHS 6) packages

-40°C to 85°C ambient operating temperature

Block Diagram

LOCK

÷2

÷1

÷2

2XQ

SYNC0

SYNC1

REF_SEL

REF

PLL

VCO

20MHz - 160MHz

FEEDBACK

nPE

PLL_EN

FREQ_SEL

÷4

nQ5

Q/2

OE/nRST

ICS870919BVI REVISION B JANUARY 10, 2012

870919BRILF Related Products

	870919BRILF	870919BVILFT	870919BRILFT
Description	Clock Generators u0026 Support Products 8-OUTPUT LVCMOS CLK GENERATOR	Clock Generators u0026 Support Products 8-OUTPUT LVCMOS CLK GENERATOR	Clock Generators u0026 Support Products 8-OUTPUT LVCMOS CLK GENERATOR
Product Category	Clock Generators & Support Products	Clock Generators & Support Products	Clock Generators & Support Products
Manufacturer	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)	IDT (Integrated Device Technology, Inc.)
RoHS	Details	Details	Details
Package / Case	QSOP-28	PLCC-28	QSOP-28
Height	1.47 mm	3.63 mm	1.47 mm
Length	9.9 mm	11.5 mm	9.9 mm
Factory Pack Quantity	48	500	2500
Width	3.8 mm	11.5 mm	3.8 mm
Packaging	Tube	Reel	Reel

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