2:1, Single-Ended Multiplexer
Data Sheet
83052I
G
ENERAL
D
ESCRIPTION
The 83052I is a low skew, 2:1, Single-ended Multiplexer. The 83052I
has two selectable single-ended clock inputs and one single-ended
clock output. The output has a V
DDO
pin which may be set at 3.3V,
2.5V, or 1.8V, making the device ideal for use in voltage trans-lation
applications. An output enable pin places the output in a high im-
pedance state which may be useful for testing or debug. The device
operates up to 250MHz and is packaged in an 8 TSSOP.
F
EATURES
• 2:1 single-ended multiplexer
• Q nominal output impedance: 15Ω (V
DDO
= 3.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 2.7ns (maximum), (V
DD
= V
DDO
= 3.3V)
• Input skew: 160ps (maximum), (V
DD
= V
DDO
= 3.3V)
• Part-to-part skew: 490ps (maximum), (V
DD
= V
DDO
= 3.3V)
•
Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz):
0.18ps (typical),
(V
DD
= V
DDO
= 3.3V)
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
CLK0
P
IN
A
SSIGNMENT
V
DDO
GND
CLK1
V
DD
1
2
3
4
8
7
6
5
Q
SEL0
CLK0
OE
CLK1
SEL0
OE
Q
83052I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
©2015 Integrated Device Technology, Inc
1
December 15, 2015
83052I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 6
4
5
7
8
Name
V
DDO
GND
CLK1, CLK0
V
DD
OE
SEL0
Q
Power
Power
Input
Power
Input
Input
Output
Type
Description
Output supply pin.
Power supply ground.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Positive supply pin.
Output enable. When LOW, outputs are in HIGH impedance state.
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Clock select input. See
Table 3. Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 1.89V
Test Conditions
Minimum
Typical
4
51
51
18
19
19
15
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Control Inputs
SEL0
0
1
Input Selected to Q
CLK0
CLK1
©2015 Integrated Device Technology, Inc
2
December 15, 2015
83052I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%, 2.5V±5%
OR
1.8V±5%,T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
1.71
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.89
40
5
Units
V
V
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5%
OR
1.8V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
1.71
Typical
2.5
2.5
1.8
Maximum
2.625
2.625
1.89
36
5
Units
V
V
V
mA
mA
©2015 Integrated Device Technology, Inc
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December 15, 2015
83052I Data Sheet
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK0, CLK1,
SEL0
OE
I
IL
Input Low Current
CLK0, CLK1,
SEL0
OE
V
OH
Output HighVoltage
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
-5
-150
2.6
1.8
V
DD
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
Input High Current
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement section, “Load Test Circuit” diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 4
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
200
45
45
0.18
700
55
2.0
2.0
2.4
2.5
36
Test Conditions
Minimum
Typical
Maximum
250
2.7
2.9
160
490
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
4
December 15, 2015
83052I Data Sheet
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 4
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
300
46
45
0.14
700
54
2.3
2.3
2.6
2.6
23
Test Conditions
Minimum
Typical
Maximum
250
2.9
2.9
106
350
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 4
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
350
46
45
0.16
850
54
2.3
2.3
3.1
3.1
19
Test Conditions
Minimum
Typical
Maximum
250
3.9
3.9
66
350
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
5
December 15, 2015
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