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DM74LS10M

Description
Logic Gates Trp 3-Input NAND Gat
Categorylogic    logic   
File Size46KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS10M Overview

Logic Gates Trp 3-Input NAND Gat

DM74LS10M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codeunknown
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.65 mm
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)3.3 mA
Prop。Delay @ Nom-Sup15 ns
propagation delay (tpd)15 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
DM74LS10 Triple 3-Input NAND Gate
August 1986
Revised March 2000
DM74LS10
Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of
which performs the logic NAND function.
Ordering Code:
Order Number
DM74LS10M
DM74LS10N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
ABC
Inputs
A
X
X
L
H
B
X
L
X
H
C
L
X
X
H
Output
Y
H
H
H
L
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
© 2000 Fairchild Semiconductor Corporation
DS006349
www.fairchildsemi.com

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