U62256AS2K10LL datasheet, PDF - EEWORLD Datasheet

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U62256AS2K10LL: Description32K X 8 STANDARD SRAM, 70 ns, PDIP28; Categorystorage; File Size150KB，10 Pages; ManufacturerETC

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U62256AS2K10LL Overview

32K X 8 STANDARD SRAM, 70 ns, PDIP28

U62256AS2K10LL Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	28
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	70 ns
Processing package description	0.600 INCH, GREEN, PLASTIC, DIP-28
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	IN-LINE
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
terminal coating	NOT SPECIFIED
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
memory width	8
organize	32K X 8
storage density	262144 deg
operating mode	ASYNCHRONOUS
Number of digits	32768 words
Number of digits	32K
Memory IC type	STANDARD SRAM
serial parallel	PARALLEL

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U62256A

Standard 32K x 8 SRAM

Features

32768x8 bit static CMOS RAM

Access times 70 ns, 100 ns

Common data inputs and

Description

The U62256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read

- Standby

- Write

- Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

The Read cycle is finished by the

falling edge of W, or by the rising

edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

data outputs

Three-state outputs

Typ. operating supply current

70 ns: 50 mA

100 ns: 40 mA

TTL/CMOS-compatible

Automatical reduction of power

dissipation in long Read Cycles

Power supply voltage 5 V + 10 %

Operating temperature ranges

0 to 70 °C

-40 to 85 °C

-40 to 125 °C

QS 9000 Quality Standard

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity >100 mA

Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Pin Configuration

Pin Description

A14

A12

DQ0

DQ1

DQ2

VSS

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A14

DQ0 - DQ7

VCC

VSS

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

PDIP

SOP

Top View

April 20, 2004

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