Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
I N F O R M A T I O N
Distinctive Characteristics
8 independent Ethernet Access Ports
Two 10/100Mbps Fast Ethernet
Ports
Direct interface with 10BaseT
transceiver
IEEE 802.3u compliant MII
(Media Independent Inter-
face) and Serial Management
interface
Direct interface with
100BaseTX, T2, T4, or TF
transceivers
Six 10Mbps Ethernet Ports
Direct interface with 10BaseT
transceiver
0.5 micron 3.3 Volt CMOS process
352-BGA package
Operating frequency
-33
-40
-50
-66
mum
33 MHz maximum
40 MHz maximum
50 MHz maximum
66.66 MHz maxi-
EA218 – 6+2 Ports Ethernet Access Controller
XpressFlow 2020 Ethernet Routing Switch Chipset
XPRESSFLOW BUS
MANAGEMENT BUS
32
16
EA-218
Local
Buffer
Memory
Local
Buffer
Memory
Interface
32
XpressFlow
Bus Interafce
Management
Bus Interafce
32
Automatic
Buffer
Manager
MAC Interface
32
MAC Port #0 to #7
Port 0
1
2
3
4
5
6
7
2-Port
100Base-Tx
PHY
6-Port
10BaseT PHY
Port 0
1
2
3
4
5
6
7
32-bit Local Buffer Memory Interface
Supports 128k to 1M bytes
Utilize high performance 32-bit
Synchronous Burst SRAM
Hardware assisted Buffer and Queue
Management
16-bit Management Bus I/O Interface
Allows host to access Control
Registers & Local Buffer Memory
Big and Little Endian CPUs
Direct interface to standard micro-
processors, including 386, 486
families and Motorola MPC series
embedded processors
32-bit
XpressFlow
Bus Interface
Uses Granule for frame transfer-
ring between Access Controllers
Unicast, multicast, and broadcast
frames
Also detects IEEE 802.3X MAC
Control frames
© 1998
Zarlink Semiconductor, Inc.
Block Diagram-
EA218 6+2 Ports Ethernet Access Controller
General Description
The EA-208 provides the Ethernet network access interface. It supports 6 ports of 10Mbps
Ethernet and 2 ports of 10/100 Mbps Ethernet. The 10Mbps ports uses serial interface to con-
nect with external 10BaseT or other 10Mbps PHY devices. For 10/100 Mbps ports, MII inter-
face is used to connect external PHY devices.
The EA-208 provides the MAC protocols, handles the local buffer memory interface and man-
agement, arbitrates among multiple priority queues, and interfaces with the
XpressFlow
Engine
and other Access Controllers through the
XpressFlow
message passing protocol.
Related Components:
SC220
– XpressFlow Engine
EA218E–
8-port 10Mb Ethernet Access Controller
EA234
– 4-port 10/100Mbps Ethernet Access Controller
1
Rev. 2.1- February, 1999
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XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
XPRESSFLOW BUS
Characteristics Continue
Works together with SC-220 Xpress-
Flow Engine
Forwards frames at full line-rate
Distributed Flow Caching™ to re-
duce frame forwarding latency
Half and Full Duplex operation
Programmable Flow Control
Jam Collision for Half Duplex
Mode
Transmit Flow Control Frame for
IEEE 802.3x Full Duplex Mode
Supports Store-&-Forward frame for-
warding mode
Multi-Media ready with QoS supports
Four frame transmission priority
queues
Complies with IEEE 802.1 Bridge
Standard
Assigns one unique MAC Address
for each port
VLAN ID Tagging & Stripping
Auto padding if necessary after
stripping
Automatic retry frame transmission
Transmit collision
Transmit buffer under-run
Automatic receive filtering for bad
frames for Store & Forward Mode
Bad FCS
Short events or frames under 64
bytes
Long events or frames over
1518/1522 bytes
Automatic statistic collection for
RMON
Buffer
RAM
Address
Mapping
Table
32
MANAGEMENT BUS
32
16
EA-218
Local
Buffer
Memory
Local
Buffer
Memory
Interface
XpressFlow
Bus Interafce
Management
Bus Interafce
32
Automatic
Buffer
Manager
MAC Interface
32
MAC Port #0 to #7
Port 0
1
2
3
4
5
6
7
2-Port
100Base-Tx
PHY
6-Port
10BaseT PHY
Port 0
1
2
3
4
5
6
7
Block Diagram –
EA218E 8-Port Ethernet Access Controller
Typical Application
:
A 22-port Ethernet Switch with 2-Fast Ethernet
RS232 Local
Control Console
Buffer
RAM
SC220
XpressFlow
Engine
Flash
ROM
Switch
Manager
CPU
DRAM
Management Bus
XpressFlow Bus
EA218E
8-Port
Ethernet
Access
Controller
Buffer
RAM
EA218E
8-Port
Ethernet
Access
Controller
Buffer
RAM
EA218
8-Port
Ethernet
Access
Controller
8 Ethernet ports
8 Ethernet ports
Six 10M Ethernet + two
100M Fast Ethernet ports
System Block Diagram --
22-Ports Ethernet Switch with 2 Fast Ethernet Up-Links
© 1998
Zarlink Semiconductor, Inc.
2
Rev. 2.1- February, 1999
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XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2
Ports 10Mb Ethernet Access Controller
1. PIN ASSIGNMENT
1.1 Logic Symbol
EA-218
L_A[18:2]
L_BWE[3:0]#
L_WE[3:0]#
L_OE[3:0]#
L_ADSC#
L_CLK
P_D[15:0]
P_A[11:1]
P_CS#
P_ADS#
P_RWC
P_BS16#
P_RDY#
P_INT
P_RST#
P_CLK
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
S_HPREQ#
S_REQ#
S_GNT#
S_CLK
4
4
4
Control Buffer
Memory Interface
L_D[31:0]
Test Pin
TEST
Tm_RXD
Tm_RXC
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
Management Bus
Interface
Port [7:2]
10M Serial Interface
4
MII Mode
10BaseT
Serial Xface
Port [1:0]
10/100 MII Interface
Mm_RXD[3:0] Tm_RXD
Mm_RXDV
Tm_RXC
Mm_RXC
Mm_RXER
Mm_TXER
Mm_TXC
Mm_TXEN
Mm_TXD[0]
Mm_TXD[1]
Mm_TXD[2]
Mm_TXD[3]
Mm_COL
Mm_CRS
Mm_LNK
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
XpressFlow
Bus Interface
MII Serial
Managem't
M_MDC
M_MDIO
© 1998
Zarlink Semiconductor, Inc.
3
Rev. 2.1- February, 1999
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XpressFlow-2020 Series –
Ethernet Switch Chipset
1.2 Pin Assignment
(Preliminary)
Note:
#
Input
In-ST
Output
Out-OD
I/O-TS
I/O-OD
5VT
EA218
6+2
Ports 10Mb Ethernet Access Controller
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Max
I
OL
/ I
OH
Name and Functions
16mA
Management Bus – Data Bit [15:0]
Pin No(s).
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
F25
H25
J24
G25
G26
H26
J26
K24
XpressFlow Bus Interface
C23,A23,B22,C22,A22
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
B12
A12
C14
C13
B23
A24
B24
A13
D13
Symbol
Type
P_D[15:0]
TTL I/O-TS (5VT)
P_A[11:1]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
S_D[31:27] /
P_C[0:4]
S_D[26:0]
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL Out-OD
TTL Out-OD
TTL In (5VT)
CMOS Output
TTL In-ST (5VT)
TTL In (5VT)
CMOS I/O-TS
CMOS I/O-TS
Management Bus – Address Bit [11:1]
Management Bus – Address Strobe
Management Bus – Read/Write Control
Management Bus – Data Ready
Management Bus – 16 bit Data Bus
Management Bus – Chip Select
Management Bus – Interrupt Request
Management Bus – Master Reset
Management Bus – Bus Clock
XpressFlow
Bus – Data Bit [31:27] or Manage-
ment Bus Interface Configuration bit [0:4]
XpressFlow
Bus – Data Bit [26:0]
16mA
16mA
4mA
12 mA
12mA
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Output
CMOS Input
CMOS Input
CMOS Input
12 mA
12mA
12 mA
12 mA
12mA
4mA
XpressFlow
Bus – Message Envelope
XpressFlow
Bus – End of Frame
XpressFlow
Bus – Initiator Ready
XpressFlow
Bus – Target Abort
XpressFlow
Bus – High Priority Request
XpressFlow
Bus – Bus Request to SC201
XpressFlow
Bus – Bus Grant from SC201
XpressFlow
Bus – Bus Overload
XpressFlow
Bus – Clock
© 1998
Zarlink Semiconductor, Inc.
4
Rev. 2.1- February, 1999
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