HD34
ADP SRAM I
o
5 Volt x8 Asynchronous Dual-Port Static RAM
Memory Configuration
4K x 8
Device
HD34
Key Features:
•
•
•
•
•
•
•
Industry leading asynchronous Dual-Port Static RAM (up to 15ns)
Simultaneous memory access through two ports
TTL compatible; 5V power supply
Available packages: 52 – pin Plastic Lead Chip Carrier (PLCC)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 15ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with conventional dual-port devices including IDT 7134 and Cypress CY7C135
Product Description:
HBA’s Asynchronous Dual-Port (ADP I) Static RAM offers industry leading 0.25um process technology and 4K x 8 memory
configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous,
asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory
using the depth and width expansion features.
These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such
as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.
5HD086A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
Page 1 of 11
HD34
ADP SRAM I
Block Diagram of Asynchronous Dual Port Static RAM
4K X 8
OE
L
CE
L
R / W
L
I/O
0-7
L
OE
R
CE
R
R / W
R
I/O
0-7 R
I/O
Control
I/O
Control
A
11 L
A
0 L
Address
Decoder
SRAM
Address
Decoder
A
11 R
A
0 R
Figure 1. Device Architecture
NC
R/W
L
CE
L
VCC
CE
R
R/W
R
NC
3
2
1
52
51
50
49
Index
7
6
5
4
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
A
11R
A
10R
48
47
46
45
44
43
42
A
0L
OE
L
A
10L
A
11L
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
PLCC-52 (Drw No: J-01A; Order Code: J)
Top View
41
40
39
38
37
36
35
34
27
28
29
30
31
32
33
NC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
52 Pin PLCC
Figure 2. Device Pin-Out
I/O
5R
I/O
6R
5HD086A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
Page 2 of 11
HD34
ADP SRAM I
Left Port
_____
Right Port
CE
R
R/W
R
OE
R
A
0R-11R
I/O
0R –7R
Vcc
_____
____
_____
Name
Chip Enable
Read / Write Enable
Output Enable
Address
Data Inputs/Outputs
Power
Ground
Symbol
Rating
Terminal Voltage with
respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Com & Ind
-0.5 to + 7.0
-55 to +125
-65 to +150
50
Unit
V
°
CE
L
R/W
L
OE
L
A
0L-11L
I/O
0L-7R
GND
_____
____
V
TERM
T
BIAS
T
STG
I
OUT
NOTES:
C
C
°
mA
Table 1. Pin Descriptions
Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended
period of operation is outside this range. Standard operation should fall within the Recommended
Operating Conditions
.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Commercial Temperature
Min.
4.5
0
2.2
-0.5
0
-
-
2.4
-
Industrial Temperature
Min.
4.5
0
2.2
-0.5
-40
-
-
2.4
-
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
70
10
10
-
0.4
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
85
10
10
-
0.4
Unit
Recommended Operating Conditions
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage Com’l/Ind’l
Input Low Voltage Com’l/Ind’l
Operating Temperature
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH=-4mA
Output Logic “0” Voltage, IOL = 4mA
V
V
V
V
°
V
IH
V
IL
T
A
I
LI
(1)
I
LO
V
OH
V
OL
C
DC Electrical Characteristics
µA
µA
V
V
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Input Capacitance
C
IN(2)
Output Capacitance
C
OUT(2)
NOTES:
Conditions
(3)
V
IN
= 3dV
V
OUT
= 3dV
Max.
11
11
Unit
pF
pF
1. At Vcc < 2.0V, input leakage is undefined.
2. This parameter is determined by device characterization but is not production tested.
3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.
5HD086A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
Page 3 of 11
HD34
ADP SRAM I
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD34L15
Typ.
Max.
240
-
60
-
150
-
4
-
125
-
HD34L25
Typ.
160
160
25
25
95
95
0.2
0.2
95
95
Unit
Max.
220
260
50
80
140
170
4
mA
10
120
150
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
170
-
25
-
105
-
0.2
-
105
-
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
NOTES:
1.
2.
1.
2.
At f=f
MAX
, address and control lines, except Output Enable, are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions of input level of GND
to 3V.
f = 0 means no address or control lines change.
Vcc = 5V, tA = +25C for Typ and is not production tested. Vcc dc = 100mA (Typ)
Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port.
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD34L35
Typ.
Max.
210
-
45
-
130
-
4
-
110
-
HD34L55
Typ.
140
-
25
-
75
-
0.2
-
75
-
Unit
Max.
200
-
40
-
130
-
4
mA
-
100
-
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
150
-
25
-
85
-
0.2
-
85
-
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
5HD086A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
Page 4 of 11
HD34
ADP SRAM I
Commercial & Industrial
HD34L15
Symbol
Read Cycle
t
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Byte Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
15
-
-
-
-
3
0
-
0
-
-
15
15
15
10
-
-
10
-
15
25
-
-
-
-
3
0
-
0
-
-
25
25
25
12
-
-
10
-
25
35
-
-
-
-
3
0
-
0
-
-
35
35
35
20
-
-
15
-
35
55
-
-
-
-
3
5
-
0
-
-
55
55
55
25
-
-
25
-
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HD34L25
Min.
Max.
HD34L35
Min.
Max.
HD34L55
Min.
Max.
Unit
Parameter
Min.
Max.
Write Cycle
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
t
WDD
t
DDD
NOTES:
1.
2.
3.
4.
Transition is meansured 500mV from Low or High-impedance voltage Output Test Load
This parameter is guaranteed by device characterization, but is not production tested.
____
For Master/Slave combination, twc = t
BAA
+ t
WP
, since R/W = VIL must occur after t
BAA
.
______
____
width must be the larger of twp or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be
If OE is LOW during a R/W controlled write cycle, the write pulse
____
______
placed on the bus for the required t
DW
. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified twp.
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1,2)
Data Hold Time
Write Enable to Output in High-Z
(1,2)
Output Active from End-of-Write
(1,2)
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
15
12
12
0
12
0
10
-
0
-
0
-
-
-
-
-
-
-
-
-
10
-
10
-
30
25
25
20
20
0
15
0
12
-
0
-
0
-
-
-
-
-
-
-
-
-
10
-
10
-
50
35
35
30
30
0
25
0
15
-
0
-
0
-
-
-
-
-
-
-
-
-
15
-
15
-
60
35
55
40
40
0
30
0
20
-
0
-
0
-
-
-
-
-
-
-
-
-
25
-
30
-
70
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3. AC Electrical Characteristics
5HD086A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
Page 5 of 11
京公网安备 11010802033920号
EEWORLD
