CAT28C257HN-12 datasheet, PDF - EEWORLD Datasheet

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CAT28C257HN-12: Description256K-Bit CMOS PARALLEL E2PROM; Categorystorage storage; File Size54KB，10 Pages; ManufacturerCatalyst; Websitehttp://www.catalyst-semiconductor.com/

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CAT28C257HN-12 Overview

256K-Bit CMOS PARALLEL E2PROM

CAT28C257HN-12 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Catalyst
package instruction	QCCJ, LDCC32,.5X.6
Reach Compliance Code	unknown
Is Samacsys	N
Maximum access time	120 ns
command user interface	NO
Data polling	YES
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
memory density	262144 bit
Memory IC Type	EEPROM
memory width	8
Number of terminals	32
word count	32768 words
character code	32000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
page size	128 words
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.00015 A
Maximum slew rate	0.03 mA
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
switch bit	YES
Base Number Matches	1

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CAT28C257

256K-Bit CMOS PARALLEL E

PROM

FEATURES

Fast Read Access Times: 90/120/150 ns

Low Power CMOS Dissipation:

Automatic Page Write Operation:

–Active: 25 mA Max.

–Standby: 150

A Max.

Simple Write Operation:

–1 to 128 Bytes in 5ms

–Page Load Timer

End of Write Detection:

–On-Chip Address and Data Latches

–Self-Timed Write Cycle with Auto-Clear

Fast Write Cycle Time:

–Toggle Bit

–DATA Polling

DATA

Hardware and Software Write Protection

100,000 Program/Erase Cycles

100 Year Data Retention

Commercial, Industrial and Automotive

–5ms Max

CMOS and TTL Compatible I/O

Temperature Ranges

DESCRIPTION

The CAT28C257 is a fast, low power, 5V-only CMOS

Parallel E

PROM organized as 32K x 8-bits. It requires a

simple interface for in-system programming. On-chip

address and data latches, self-timed write cycle with auto-

clear and V

power up/down write protection eliminate

additional timing and protection hardware.

DATA

Polling

and Toggle status bits signal the start and end of the self-

timed write cycle. Additionally, the CAT28C257 features

hardware and software write protection.

The CAT28C257 is manufactured using Catalyst’s ad-

vanced CMOS floating gate technology. It is designed to

endure 100,000 program/erase cycles and has a data

retention of 100 years. The device is available in JEDEC

approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC

packages.

BLOCK DIAGRAM

32,768 x 8

PROM

ARRAY

128 BYTE PAGE

A7–A14

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

ROW

DECODER

VCC

HIGH VOLTAGE

GENERATOR

CONTROL

LOGIC

I/O BUFFERS

TIMER

DATA POLLING

AND

TOGGLE BIT

COLUMN

DECODER

5096 FHD F02

I/O0–I/O7

A0–A6

ADDR. BUFFER

& LATCHES

Characteristics subject to change without notice

Doc. No. 25073-00 2/98

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