K7I320882M-FC25 datasheet, PDF

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K7I320882M-FC25: DescriptionDDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size181KB，18 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7I320882M-FC25 Overview

DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

K7I320882M-FC25 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	33554432 bit
Memory IC Type	DDR SRAM
memory width	8
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.2 A
Minimum standby current	1.7 V
Maximum slew rate	0.54 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

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K7I323682M

K7I321882M

K7I320882M

Document Title

Preliminary

1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM

1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM

Revision History

Rev. No.

0.0

0.1

History

1. Initial document.

Pin name change from DLL to Doff.

Vddq range change from 1.5V to 1.5V~1.8V.

Update JTAG test conditions.

Reserved pin for high density name change from NC to Vss/SA

Delete AC test condition about Clock Input timing Reference Level

Delete clock description on page 2 and add HSTL I/O comment

Draft Date

October, 22 2001

December, 12 2001

Remark

Advance

Preliminary

0.2

1. Update current characteristics in DC electrical characteristics

2. Change AC timing characteristics

3. Update JTAG instruction coding and diagrams

1. Add AC electrical characteristics.

2. Change AC timing characteristics.

3. Change DC electrical characteristics(I

SB1

)

Change the data Setup/Hold time.

Change the Access Time.(tCHQV, tCHQX, etc.)

Change the Clock Cycle Time.(MAX value of tKHKH)

Change the JTAG instruction coding.

July, 29. 2002

Preliminary

0.3

Sep. 6. 2002

Preliminary

0.4

Oct. 7. 2002

Preliminary

0.5

1. Change the Boundary scan exit order.

2. Change the AC timing characteristics(-25, -20)

3. Correct the Overshoot and Undershoot timing diagrams.

Dec. 16, 2002

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

Dec. 2002

Rev 0.5

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