73M2901CE
V.22bis Single Chip Modem
APRIL 2004
DESCRIPTION
The 73M2901CE low speed modem integrates a
data pump, controller, and analog front end in a 3.3V
device with a powerful "AT" command host
interface. The modem reduces external component
count/cost by incorporating many features like
parallel phone detect, Line-In-Use and Ring
detection in software without additional components
required.
The device is a "one chip fits all” solution for
applications including set-top boxes, point-of-sale
terminals, automatic teller machines, utility meters,
vending machines and smart card readers.
Another distinctive feature of this device is pin
compatibility with TDK’s flagship embedded hard
modems, the 73M2901CL, and the 73M1903 soft
modem AFE. This offers customers a cost effective
method to design for both hard or soft modem
solutions in the same system as a risk-free cost
reduction path.
Complete Support and Modem Reference Designs
Error correction software and support are part of the
solution offered by TDK Semiconductor. Our in-
house application engineering team is here to help
you meet your international certification needs.
FEATURES
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True one chip solution for embedded systems
As low as 9.5mA operating with standby and
power down mode available
Power supply operation from 3.6V to 2.7V
Data speed:
V.22bis – 2400bps
V.22/Bell212 – 1200bps
V.21/Bell103 – 300bps
V.23 – 1200/75bps (with PAVI turnaround)
Bell202 – 1200bps
Bell202/V23 4-wire operation
International Call Progress support
FCC68, CTR21, JATE, etc.
Worldwide Caller ID capability
Type I and II support
EIA 777 compliant
DTMF generation and detection
SMS messaging support
On chip hybrid driver
Blacklisting capability
Line-In-Use and Parallel Pick-Up (911) detection
with voltage or low cost energy detection method
Incoming ring energy detection through CID path;
no optocoupler required
Manufacturing Self Test capability
Backward compatible with 73M2901CL
Packaging:
32 lead QFN
32 pin TQFP packages
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BLOCK DIAGRAM
©
2004 TDK Semiconductor Corporation
04/15/04- V2.2.1
1
73M2901CE
V.22bis Single Chip Modem
HARDWARE DESCRIPTION
The 73M2901CE is designed to operate from a +3.6
to +2.7 volt supply with low power consumption
(~30mW @3.0 volts). The modem supports
automatic standby idle mode. The modem will also
accept a request to power down from the DTE via
hardware control. No additional m
ajor components
are required to complete the modem core logic. The
modem provides direct firmware LED support via
port pins.
HARDWARE FEATURES
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•
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Fully self-contained. “AT” Command interpreter
and data pump
User pins available
Synchronous serial data I/O available
Asynchronous serial port
On-chip hybrid and line driver.
Autobaud capability from 300bps to 9600bps
Reduced external hardware support required
with energy incoming ring detection.
INTERRUPT PINS
The external interrupt sources,
DTR
and
RING,
come
from dedicated input pins of the same name.
DTR informs the 73M2901CE that the host has
requested the 73M2901CE perform a specific
function. The function of
DTR
can be changed by
“AT” commands (described in full in the TDK
73M2901CE User’s Guide).
RING
is used to inform the 73M2901CE that the
external DAA circuitry or ring energy detector has
detected a ring signal. It will go active when each
“RING” message is sent on RXD.
In addition, sending any character on the TXD line
also generates an internal interrupt.
CRYSTAL OSCILLATOR
The TDK 73M2901CE single chip modem can use
an external 11.0592 MHz reference clock or can
generate a clock using only a crystal and two
capacitors. If an external clock is used, it should be
applied to OSCIN.
but no clocks will be supplied to the CPU. Instruction
processing and activity on the internal busses is
halted. Normal operation is resumed when an
interruption such as assertion of
DTR
or
RING,
a
character is sent to the 73M2901CE TXD input, or a
reset occurs.
ANALOG LINE / HYBRID INTERFACE
The 73M2901CE provides a differential analog
output (TXAP and TXAN) and a single-ended analog
input (RXA) with internal A/D and D/A converters. A
driver is provided for an internal hybrid function.
The internal hybrid driver is capable of driving an
external load matching impedance and a line-
coupling transformer. The internal hybrid/line driver
senses the load and adapts itself to its requirements.
The 73M2901CE provides firmware control for a
hook relay driver (RELAY) as well as interrupt
support for a ring detect opto-coupler (RING).
POWER SUPPLY
Power is supplied to the 73M2901CE via the VPD
and VPA pins. The 73M2901CE is designed for a
single +3.6 to +2.7 volt supply and for low power
consumption (~30mW @ 3.0 volts). Ground is
supplied to the 73M2901CE via VND and VNA pins.
The 73M2901CE has been designed with separated
analog and digital supplies to insure the best
performance of the part by using separately filtered
power supplies. It is recommended that separate
locally bypassed traces be used to apply power to
the analog supply VPA and the digital supply VPD.
LOW POWER MODE
The TDK 73M2901CE supports a low power standby
mode. If the low power standby option is enabled the
73M2901CE will go into a power saving mode when
idle. The oscillator will be running, clocks will be
supplied to the UART, timers and interrupt blocks;
©
2004 TDK Semiconductor Corporation
04/15/04- V2.2.1
2
73M2901CE
V.22bis Single Chip Modem
SPECIFYING A CRYSTAL
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TDK 73M2901CE modem requires a parallel
mode
(anti-resonant) crystal, the important
specifications of which are as follows:
Mode: Parallel (anti-resonant)
Frequency: 11.0592 MHz
Frequency tolerance: ±50 ppm at initial temperature.
Temp. drift: An additional ±50 ppm over full range.
Load capacitance: 18pF to 22pF
ESR: 75Ω max.
Drive level: Less than 1mW.
The peak voltage level of the oscillator should be
checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins. A
resistor in series with the crystal can be used, if
necessary, to reduce the oscillator’s peak voltage
levels.
Crystals with low ESRs may oscillate at higher than
specified voltage levels.
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3
µs.
At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals
DCD, CTS
and
DSR
will be held inactive
for 25ms, acknowledging the reset operation, within
a 250ms time window after the reset -triggering
event. The 73M2901CE is ready for operation after
the 250ms window and/or after the signals
DCD, CTS
and
DSR
become active.
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSB shifted in and out first) and the
TXCLK and RXCLK serial synchronous clock
outputs associated with the data pins;
CTS/RTS
flow
control;
DCD, DSR
and
DTR.
In asynchronous mode,
the data is passed at the bit rate (tolerance is +1%, -
2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN
NAME
VPA
VNA
VPD
VND
PIN
10
16
2, 20, 25
1, 17, 22
TYPE
I
I
I
I
DESCRIPTION
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
ANALOG INTERFACE PIN DESCRIPTION
PIN
NAME
RXA
TXAN
TXAP
VBG
VREF
PIN
15
11
12
14
13
TYPE
I
O
O
O
O
DESCRIPTION
Receive Analog input
Transmit Analog - output
Transmit Analog + output
Analog Band Gap voltage reference (0.1µF to
VNA). This pin must not be connected to external
circuitry other than the decoupling capacitor.
Analog reference voltage (0.1µF to VNA)
©
2004 TDK Semiconductor Corporation
04/15/04- V2.2.1
3
73M2901CE
V.22bis Single Chip Modem
DIGITAL INTERFACE PIN DESCRIPTION
PIN
NAME
RESET
RXCLK
TXCLK
TXD
RXD
USR10
PIN
9
27
24
23
26
8
TYPE
I
O
O
I
O
I/O
DESCRIPTION
Reset
Receive data synchronous clock valid on rising
edge
Transmit data synchronous clock valid on rising
edge
Serial data input from DTE
Serial output to DTE
Programmable I/O port. This pin optionally be
used to control an external switch for external Line
In Use circuitry.
Programmable I/O port. This pin can optionally be
used to control an external switch for caller ID
operation.
Request to send
Clear to send
Data set ready
Data carrier detect
Ring indicator
Relay driver output
Programmable I/O port
USR11
RTS
CTS
DSR
DCD
RI
RELAY
USR20
7
6
5
4
3
32
31
29
I/O
I
O
O
O
O
O
I/O
EXTERNAL INTERRUPTS PIN DESCRIPTION
PIN
NAME
RING
DTR
PIN
30
28
TYPE
I
I
DESCRIPTION
External interrupt – Line interface ring detection
circuitry input
External interrupt – DTE DTR signal input
OSCILLATOR PIN DESCRIPTION
PIN
NAME
OSCIN
OSCOUT
PIN
19
18
TYPE
I
O
DESCRIPTION
Crystal input for internal oscillator, also input for
external source
Crystal oscillator output
©
2004 TDK Semiconductor Corporation
04/15/04- V2.2.1
4
73M2901CE
V.22bis Single Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Pin Input Voltage (except OSCIN)
Pin Input Voltage (OSCIN)
Storage Temperature
RATING
-0.5V to +4.0V
-0.5V to + 6.0V
-0.5V to VPD + 0.5V
-55ºC to 150ºC
NOTE: This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Oscillator Frequency
Operating Temperature
RECEIVER
PARAMETER
Carrier detect On
Carrier detect Off
Carrier Detect Hysteresis
Receive Level
Idle channel noise
Input impedance
Receive Gain Boost
Max Input Level at RXA
Total Harmonic Distortion
(THD)
CONDITIONS
Tip and Ring
Tip and Ring
Tip and Ring
Tip and Ring
0.2KHz – 4.0KHz
RXA
S110 bit 5=1, CID mode
Vref=1.25V
1KHz 450mVpk on RXA
THD=2 and 3 harmonic
nd
rd
RATING
2.7V – 3.6V
11.0592MHz +/- 50ppm
-40ºC to 85ºC
MIN
-43
-48
NOM
MAX
UNIT
dBm0
*
dBm0
*
2
-43
-70
150
18.8
0.587
19.3
0.622
-70
19.8
0.658
-50
-9
-65
dB
dBm0
*
dB
kΩ
dB
Vpk
dB
*
dBm0 refers to the TDK recommended line interface (8dB loss from transmit pins to the line and 5dB loss from the line to the receiver pin). Results
may vary depending on the selected DAA components. 0dBm=0.775mV
rms
; dBm=10log(V
rms2
/(1mW)(600Ω ))
©
2004 TDK Semiconductor Corporation
04/15/04- V2.2.1
5
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