ADP3421JRU-REEL7 datasheet, PDF

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ADP3421JRU-REEL7: DescriptionIC SWITCHING CONTROLLER, PDSO28, TSSOP-28, Switching Regulator or Controller; CategoryPower/power management The power supply circuit; File Size144KB，12 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADP3421JRU-REEL7 Overview

IC SWITCHING CONTROLLER, PDSO28, TSSOP-28, Switching Regulator or Controller

ADP3421JRU-REEL7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ADI
Parts packaging code	SSOP
package instruction	TSSOP-28
Contacts	28
Reach Compliance Code	not_compliant
ECCN code	EAR99
Analog Integrated Circuits - Other Types	SWITCHING CONTROLLER
control mode	VOLTAGE-MODE
Maximum input voltage	5 V
Minimum input voltage	3 V
Nominal input voltage	3.3 V
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	9.7 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	28
Maximum operating temperature	100 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP28,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.2 mm
surface mount	YES
Switch configuration	SINGLE
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

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Geyserville-Enabled DC-DC

Converter Controller for Mobile CPUs

ADP3421

FUNCTIONAL BLOCK DIAGRAM

ADP3421

DACOUT

VID4

VID3

VID2

VID1

VID0

VID DAC

CURRENT

LIMIT

COMPARATOR

LTO

LTB

LTI

CORE CONTROLLER

CLKDRV

CLKFB

IODRV

CLOCK LDO

CONTROLLER

LEVEL

TRANSLATOR

CORE

COMPARATOR

CS+

CS–

VHYS

REG

RAMP

OUT

FEATURES

Meets Intel

Mobile Voltage Positioning Requirements

Lowest Processor Dissipation for Longest Battery Life

Best Transient Containment

Minimum Number of Output Capacitors

System Power Management Compliant

Fast, Smooth Output Transition During VID Code

Change

Programmable Current Limit

Power Good

Integrated LDO Controllers for Clock and I/O Supplies

Programmable UVLO

Soft Start with Restart Lock-In

APPLICATIONS

Geyserville-Enabled Core DC-DC Converters

Fixed Voltage Mobile CPU Core DC-DC Converters

Notebook/Laptop Power Supplies

Programmable Output Power Supplies

CLSET

SSC

SOFT START

TIMER

AND

POWER GOOD

GENERATOR

SSL

CORE

GENERAL DESCRIPTION

The ADP3421 is a hysteretic dc-dc buck converter controller

with two auxiliary linear regulator controllers. The ADP3421

provides a total power conversion control solution for a micro-

processor by delivering the core, I/O, and clock voltages. The

optimized low-voltage design is powered from the 3.3 V system

supply and draws only 10

µA

maximum in shutdown. The main

output voltage is set by a 5-bit VID code. To accommodate the

transition time required by the newest processors for on-the-

fly VID changes, the ADP3421 features high-speed operation

to allow a minimized inductor size that results in the fastest change

of current to the output. To further allow for the minimum

number of output capacitors to be used, the ADP3421 features

active voltage positioning that can be optimally compensated

to ensure a superior load transient response. The main output

signal interfaces with the ADP3410 dual MOSFET driver,

which is optimized for high speed and high efﬁciency for driving

both the upper and lower (synchronous) MOSFETs of the

buck converter.

IOFB

I/O LDO

CONTROLLER

BIAS AND

REFERENCE

BIAS EN

UVLO

VCC

VIN/VCC

MONITOR AND

UVLO BIAS

REFERENCE

CONTROLLER

PWRGD

GND

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

ADP3421

Mnemonic

PWRGD

Function

Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.

Power Good Output. This signal will go high only when the

pin is high to allow IC operation, the UVLO

and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where

soft start is completed, and the voltage at the CORE pin is within the speciﬁed limits of the programmed VID

voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up

the core and linear outputs should all be in regulation before PWRGD is asserted.

Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin

voltage is below a speciﬁed threshold, the IC enters into UVLO mode regardless of the status of

SD.

When

in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor

divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.

Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source

to control the ramp-up rates of the linear regulators.

Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to

control the ramp-up rate of the core voltage.

Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good veriﬁcation.

VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output

voltage regulation.

Ground

Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN

pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.

Power Supply

Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/

source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this

pin to set the hysteresis for the hysteretic control.

Regulation Voltage Summing Input. In the recommended conﬁguration, the DACOUT voltage and the core

voltage are summed at this pin to establish regulation with output voltage positioning.

Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.

Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense

resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative

than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced

to two-thirds of its previous value, producing a current limit hysteresis.

UVLO

SSL

SSC

CORE

DACOUT

GND

OUT

VCC

RAMP

REG

CS+

CS–

REV. A

–5–

ADP3421JRU-REEL7 Related Products

	ADP3421JRU-REEL7	ADP3421JRU-REEL
Description	IC SWITCHING CONTROLLER, PDSO28, TSSOP-28, Switching Regulator or Controller	IC SWITCHING CONTROLLER, PDSO28, TSSOP-28, Switching Regulator or Controller
Is it Rohs certified?	incompatible	incompatible
Maker	ADI	ADI
Parts packaging code	SSOP	SSOP
package instruction	TSSOP-28	TSSOP-28
Contacts	28	28
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
Analog Integrated Circuits - Other Types	SWITCHING CONTROLLER	SWITCHING CONTROLLER
control mode	VOLTAGE-MODE	VOLTAGE-MODE
Maximum input voltage	5 V	5 V
Minimum input voltage	3 V	3 V
Nominal input voltage	3.3 V	3.3 V
JESD-30 code	R-PDSO-G28	R-PDSO-G28
JESD-609 code	e0	e0
length	9.7 mm	9.7 mm
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	28	28
Maximum operating temperature	100 °C	100 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP28,.25	TSSOP28,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	240
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
surface mount	YES	YES
Switch configuration	SINGLE	SINGLE
Temperature level	OTHER	OTHER
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm
Base Number Matches	1	1

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