a
Geyserville-Enabled DC-DC
Converter Controller for Mobile CPUs
ADP3421
FUNCTIONAL BLOCK DIAGRAM
ADP3421
DACOUT
VID4
VID3
VID2
VID1
VID0
VID DAC
CURRENT
LIMIT
COMPARATOR
EN
LTO
LTB
LTI
CORE CONTROLLER
CLKDRV
CLKFB
IODRV
CLOCK LDO
CONTROLLER
LEVEL
TRANSLATOR
CORE
COMPARATOR
CS+
CS–
VHYS
REG
RAMP
OUT
FEATURES
Meets Intel
®
Mobile Voltage Positioning Requirements
Lowest Processor Dissipation for Longest Battery Life
Best Transient Containment
Minimum Number of Output Capacitors
System Power Management Compliant
Fast, Smooth Output Transition During VID Code
Change
Programmable Current Limit
Power Good
Integrated LDO Controllers for Clock and I/O Supplies
Programmable UVLO
Soft Start with Restart Lock-In
APPLICATIONS
Geyserville-Enabled Core DC-DC Converters
Fixed Voltage Mobile CPU Core DC-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
CLSET
SSC
SOFT START
TIMER
AND
POWER GOOD
GENERATOR
SSL
CORE
GENERAL DESCRIPTION
The ADP3421 is a hysteretic dc-dc buck converter controller
with two auxiliary linear regulator controllers. The ADP3421
provides a total power conversion control solution for a micro-
processor by delivering the core, I/O, and clock voltages. The
optimized low-voltage design is powered from the 3.3 V system
supply and draws only 10
µA
maximum in shutdown. The main
output voltage is set by a 5-bit VID code. To accommodate the
transition time required by the newest processors for on-the-
fly VID changes, the ADP3421 features high-speed operation
to allow a minimized inductor size that results in the fastest change
of current to the output. To further allow for the minimum
number of output capacitors to be used, the ADP3421 features
active voltage positioning that can be optimally compensated
to ensure a superior load transient response. The main output
signal interfaces with the ADP3410 dual MOSFET driver,
which is optimized for high speed and high efficiency for driving
both the upper and lower (synchronous) MOSFETs of the
buck converter.
IOFB
I/O LDO
CONTROLLER
BIAS AND
REFERENCE
BIAS EN
UVLO
VCC
VIN/VCC
MONITOR AND
UVLO BIAS
REFERENCE
CONTROLLER
PWRGD
GND
SD
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADP3421–SPECIFICATIONS
Parameter
SUPPLY-UVLO-POWER GOOD
Supply Current
Symbol
I
CC(ON)
I
CC(UVLO)
V
CCH
I
CCH
V
CCL
V
CCHYS
V
UVLOTH
I
UVLO
V
SDTH
V
COREH(UP)1
V
COREH(DN)2
V
COREL(UP)1
V
COREL(DN)2
V
PWRGD3
1
(0 C
T
A
100 C, VCC = 3.3 V, V
SD
= VCC, V
ULVO
= 2.0 V, V
CORE
= V
DAC
, R
OUT
= 100
k , C
OUT
= 10 pF, C
SSC
= 1.8 nF, C
SSL
= 1.3 nF, C
LTB
= 1.5 nF, unless otherwise noted.)
Min
Typ
7
Max
15
350
10
2.9
Unit
mA
µA
µA
V
V
mV
V
µA
µA
V
V
V
V
V
V
V
V
µA
mA
mV
V
V
µA
V
%
µs
mV
µA
Conditions
V
UVLO
= 0.2 V
V
SD
= 0 V, 3.0 V
≤
VCC
≤
3.6 V
2.7
20
1.175
1.225
–0.3
0.6
1.0
0.8
1.10
×
V
DAC
1.08
×
V
DAC
0.90
×
V
DAC
0.88
×
V
DAC
0.95
×
VCC
0
0
–0.6
0.3
1.53
0.8
10
0.925
–0.85
–1.0
1.0
150
1.70
VCC UVLO Threshold
VCC UVLO Hysteresis
Battery UVLO Threshold
Battery UVLO Hysteresis
Shutdown Input Threshold
Core Power Good Threshold
V
UVLO
= 1.275 V
V
UVLO
= 1.175 V
3.0 V < VCC < 5.0 V
0.925 V < V
DAC
< 2.000 V
PWRGD Output Voltage
V
CORE
= V
DAC
V
CORE
= 0.8 V
DAC
V
UVLO
= 0.2 V
V
SSC
= 0 V
V
SSC
= 1.7 V, V
UVLO
= 1.1 V
1.275
+0.3
1.4
0.7
×
VCC
1.12
×
V
DAC
1.10
×
V
DAC
0.92
×
V
DAC
0.90
×
V
DAC
VCC
0.8
0.4
–1.4
400
1.87
0.7
×
VCC
40
2.000
0.85
35
+3
+2
CORE CONVERTER SOFT-START TIMER
Timing Charge Current
I
SSC(UP)
Discharge Current
I
SSC(DN)
Enable Threshold
V
SSCEN4
Termination Threshold
V
SSCTH
VID DAC
VID Input Threshold
VID Input Pull-Up Current
Nominal Output Voltage
Output Voltage Accuracy
Output Voltage Settling Time
CORE COMPARATOR
Input Offset Voltage
Input Bias Current
Hysteresis Current
V
VID0..4
I
VID0..4
V
DAC
∆V
DAC
/V
DAC
t
DACS5
V
COREOS
I
REG
I
RAMP
See VID Code Table I
V
REG
= 1.3 V
V
REG
= V
RAMP
= 1.3 V
V
CORE
= V
RAMP
= 1.3 V
V
CS–
= 1.30 V, V
CS+
= 1.28 V
V
REG
= 1.28 V
R
VHYS
Open
R
VHYS
= 170 kΩ
R
VHYS
= 17 kΩ
V
REG
= 1.32 V
R
VHYS
Open
R
VHYS
= 170 kΩ
R
VHYS
= 17 kΩ
VCC = 3.0 V
VCC = 3.6 V
T
A
= 25°C
0°C
≤
T
A
≤
100°C
–3
–2
–2
–7
–82
–2
7
82
1.53
2.5
0
–10
–97
+2
–13
–113
+2
13
113
1.87
3.0
0.4
20
30
10
µA
µA
µA
µA
µA
µA
V
V
V
ns
ns
ns
Hysteresis Setting Reference Voltage V
VHYS
Output Voltage
V
OUTH
V
OUTL
t
COREPD7
Propagation Delay Time
6
Rise and Fall Time
6
t
CORER8
,
t
COREF8
10
97
1.70
7
–2–
REV. A
ADP3421
Parameter
CURRENT LIMIT COMPARATOR
Input Offset Voltage
Input Bias Current
Hysteresis Current
Symbol
V
CLOS
I
CL+
I
CL–
Conditions
V
CS–
= 1.3 V
V
CS+
= 1.3 V
V
CORE
= V
RAMP
= 1.3 V
V
REG
= 1.28 V, V
CS–
= 1.3 V
V
CS+
= 1.28 V
R
IHYS
Open
R
IHYS
= 170 kΩ
R
IHYS
= 17 kΩ
V
CS+
= 1.32 V
R
IHYS
Open
R
IHYS
= 170 kΩ
R
IHYS
= 17 kΩ
T
A
= 25°C
0°C
≤
T
A
≤
100°C
V
SSC
= 0 V
V
SSC
= 1.7 V, V
UVLO
= 1.1 V
–0.6
0.3
1.53
V
CLKFB
= 2.5 V
V
CLKDRV
= 2.55 V
V
CLKDRV
= 2.45 V
∆I
CLKDRV
= 1 mA
V
IOFB
= 1.5 V
V
IODRV
= 1.53 V
V
IODRV
= 1.47 V
∆I
CLKDRV
= 1 mA
I
LTI
= –10
µA
I
LTI
= –10
µA
9
V
LTI
= 0.175 V
9
Min
–6
–5
Typ
Max
+6
+5
Unit
mV
µA
–22
–265
–30
–300
–5
–38
–335
–5
–27
–225
1.87
60
100
–1.4
400
1.87
25
1
20
µA
µA
µA
µA
µA
µA
V
ns
ns
µA
mA
mV
V
µA
µA
mA
mA/V
µA
µA
mA
mA/V
V
V
mV
ns
Hysteresis Setting Reference Voltage V
VHYS
Propagation Delay Time
6
t
CLPD7
LINEAR REGULATOR SOFT-START TIMER
Charge Current
I
SSC(UP)
Discharge Current
I
SSC(DN)
Enable Threshold
V
SSCEN4
Termination Threshold
V
SSCTH
2.5 V CLK LDO CONTROLLER
Feedback Bias Current
Output Drive Current
DC Transconductance
1.5 V I/O LDO CONTROLLER
Feedback Bias Current
Output Drive Current
DC Transconductance
LEVEL TRANSLATOR
Input Clamping Threshold
Output Voltage
Propagation Delay Time
6
I
CLKFB
I
CLKDRV
G
CLK
I
IOFB
I
IODRV
G
IO
V
LTIH
V
LTOH
V
LTOL
t
LTPD
–13
–175
1.53
–20
–200
1.70
30
50
–1.0
1.0
150
1.70
12.5
3
500
7.5
10
650
0.95
0.9
×
V
CCLT
15
1
60
1.5
V
CCLT
375
10
NOTES
1
V
CORE
ramps up monotonically.
2
V
CORE
ramps down monotonically.
3
During latency time of VID code change, the Power Good output signal should not be considered valid.
4
Internal bias and soft start are not enabled unless the soft-start pin voltage first drops below the enable threshold.
5
Measured from 50% of VID code transient amplitude to the point where V
DAC
settles within
±
1% of its steady state value.
6
Guaranteed by characterization.
7
40 mV p-p amplitude impulse with 20 mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing.
8
Measured between the 30% and 70% points of the output voltage swing.
9
The LTO output tied to V
CCLT
= 2.5 V rail through an R
LTO
= 150
Ω
pull-up resistor.
Specifications subject to change without notice.
REV. A
–3–
ADP3421
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
VHYS
1
CLSET
2
28
27
26
25
24
Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V
UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CS–
CS+
REG
RAMP
VCC
OUT
LTO
3
LTI
4
LTB
5
VID4
6
VID3
7
ADP3421
23
22
GND
TOP VIEW
VID2
8
(Not to Scale)
21
DACOUT
VID1
9
VID0
10
CLKDRV
11
CLKFB
12
20
19
18
17
16
15
CORE
SSC
SSL
UVLO
PWRGD
SD
ORDERING GUIDE
IODRV
13
Model
Temperature
Range
Package
Description
Package
Option
IOFB
14
ADP3421JRU 0°C to 100°C
Thin Shrink Small RU-28
Outline (TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
WARNING!
ESD SENSITIVE DEVICE
Pin
1
2
Mnemonic
VHYS
CLSET
Function
Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to
ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin.
Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs
a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not
triggered.
Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the
output high level. That voltage cannot be less than 1.5 V.
Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is
provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the
LTI pin reaches 1.5 V.
Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be by-
passed to ground with a large value capacitor.
VID Input. Most significant bit.
VID Input
VID Input
VID Input
VID Input. Least significant bit.
2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the CLKFB node regulated at 2.5 V.
2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the CLKDRV pin.
1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the IOFB node regulated at 1.5 V.
1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the IODRV pin.
3
4
LTO
LTI
5
6
7
8
9
10
11
12
13
14
LTB
VID4
VID3
VID2
VID1
VID0
CLKDRV
CLKFB
IODRV
IOFB
–4–
REV. A
ADP3421
Pin
15
16
Mnemonic
SD
PWRGD
Function
Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.
Power Good Output. This signal will go high only when the
SD
pin is high to allow IC operation, the UVLO
and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where
soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID
voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up
the core and linear outputs should all be in regulation before PWRGD is asserted.
Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin
voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of
SD.
When
in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor
divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.
Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source
to control the ramp-up rates of the linear regulators.
Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to
control the ramp-up rate of the core voltage.
Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good verification.
VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output
voltage regulation.
Ground
Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN
pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.
Power Supply
Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/
source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this
pin to set the hysteresis for the hysteretic control.
Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core
voltage are summed at this pin to establish regulation with output voltage positioning.
Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.
Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense
resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative
than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced
to two-thirds of its previous value, producing a current limit hysteresis.
17
UVLO
18
19
20
21
22
23
24
25
SSL
SSC
CORE
DACOUT
GND
OUT
VCC
RAMP
26
27
28
REG
CS+
CS–
REV. A
–5–
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