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54HST109NS

Description
J-Kbar Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, DIE
Categorylogic    logic   
File Size2MB,84 Pages
ManufacturerDynex
Websitehttp://www.dynexsemi.com/
Download Datasheet Parametric View All

54HST109NS Overview

J-Kbar Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, DIE

54HST109NS Parametric

Parameter NameAttribute value
Parts packaging codeDIE
package instructionDIE,
Reach Compliance Codeunknown
Other featuresRADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
seriesHST/T
JESD-30 codeX-XUUC-N
Logic integrated circuit typeJ-KBAR FLIP-FLOP
Number of digits2
Number of functions2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialUNSPECIFIED
encapsulated codeDIE
Package shapeUNSPECIFIED
Package formUNCASED CHIP
propagation delay (tpd)25 ns
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal locationUPPER
Trigger typePOSITIVE EDGE
Base Number Matches1
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