INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4720B
HEF4720V
LSI
256-bit, 1-bit per word random
access memories
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
256-bit, 1-bit per word random access memories
DESCRIPTION
The HEF4720B and HEF4720V are 256-bit, 1-bit per word
random access memories with 3-state outputs. The
memories are fully decoded and completely static.
Recommended supply voltage range for HEF4720B is 3 to
15 V and for HEF4720V is 4,5 to 12,5 V; minimum
stand-by voltage for both types is 3 V.
The use of LOCMOS gives the added advantage of very
low stand-by power. The circuits can be directly interfaced
with standard bipolar devices (TTL) without using special
HEF4720B
HEF4720V
interface circuits. The memory operates from a single
power supply. The separate chip select input (CS) allows
simple memory expansion when the outputs are wire-O
Red. If CS is HIGH, the outputs are floating and no new
information can be written into the memory. The signal at
O has the same polarity as the data input D, while the
signal at O is the complement of the signal at O. The write
control W must be HIGH for writing into the memory.
Fig.1 Functional diagram.
HEF4720BP; HEF4720VP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4720BD; HEF4720VD(F): 16-lead DIL; ceramic
(cerdip) (SOT74)
HEF4720BT;
HEF4720VT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA
See Family Specifications.
January 1995
2
Philips Semiconductors
Product specification
256-bit, 1-bit per word random access memories
I
DD
LIMITS
See below.
FUNCTION TABLE
CS
L
L
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance OFF-state
W
H
L
X
O
data written
into memory
data written
into memory
Z
O
complement of data
written into memory
complement of data
written into memory
Z
inhibit
read
MODE
write
PINNING
CS
W
D
A
0
to A
7
O
O
HEF4720B
HEF4720V
chip select input (active LOW)
write enable input
data input
address inputs
3-state output (active HIGH)
3-state output (active LOW)
SUPPLY VOLTAGE
RATING
HEF4720B
HEF4720V
−0,5
to 18
−0,5
to 18
RECOMMENDED OPERATING
3,0 to 15,0
4,5 to 12,5
STAND-BY MIN.
3
3
V
V
The values given at V
DD
= 15 V in the following DC and
AC characteristics, are not applicable to the HEF4720V,
because of its lower supply voltage range.
DC CHARACTERISTICS
V
SS
= 0 V
T
amb
(°C)
V
DD
V
Output current
LOW
Quiescent device
current
Input leakage current
HEF4720V
HEF4720B
10
15
±I
IN
0,3
0,3
0,3
0,3
1
µA
1
µA
4,75
10
15
5
10
15
I
DD
V
OL
V
0,4
0,5
1,5
I
OL
SYMBOL
−40
MIN.
2,4
4,8
10,0
25
50
100
+25
+85
MIN.
1,6
3,2
7,5
25
50
100
MAX.
mA
mA
mA
200
µA
400
µA
800
µA
MAX. MIN. MAX.
2
4
10
January 1995
3
FPGA/CPLD
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