HFA3861
ADVANCE INFORMATION
Data Sheet
July 1999
File Number
4699.1
Direct Sequence Spread Spectrum
Baseband Processor
The Intersil HFA3861 Direct Sequence
Spread Spectrum (DSSS) baseband
processor is part of the PRISM®
2.4GHz radio chipset, and contains all
the functions necessary for a full or half duplex packet
baseband transceiver.
™
Features
• Complete DSSS Baseband Processor
• Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant
• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm
• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V
• Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK
• Supports Full or Half Duplex Operations
• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
• Targeted for Multipath Delay Spreads ~100ns
• Supports Short Preamble Acquisition
The HFA3861 has on-board A/D’s for analog I and Q inputs
and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling
capability, are available along with Complementary Code
Keying to provide a variety of data rates. Built-in flexibility
allows the HFA3861 to be configured through a general
purpose control bus, for a range of applications. Both
Receive and Transmit AGC functions with 7-bit AGC control
obtain maximum performance in the analog portions of the
transceiver. The HFA3861 is housed in a thin plastic quad
flat package (TQFP) suitable for PCMCIA board
applications.
Applications
• Enterprise WLAN Systems
• Systems Targeting IEEE 802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
Ordering Information
PART NO.
HFA3861IV
HFA3861IV96
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
PKG. TYPE
64 Ld TQFP
Tape and Reel
PKG. NO.
Q64.10x10
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable PDA/Notebook Computer
• Wireless Digital Audio, Video, Multimedia
Pinout
SDI
RESET
TX_PE
RX_PE
CCA
TX_RDY
TXD
V
DDD
GNDd
TXCLK
MD_RDY
RXD
RXCLK
TEST7
TEST6
TEST5
• PCN/Wireless PBX
• Wireless Bridges
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GNDd
V
DDD
SD
SCLK
R/W
CS
GNDd
V
DDD
GNDa
RX_I+
RX_I-
V
DDA
RX_Q+
RX_Q-
GNDa
V
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V
DDA
TX_AGC_IN
RX-IF_DET
GNDa
I
REF
V
DDA
TX_I+
TX_I-
GNDa
COMPCAP2
COMPRES2
GNDa
TX_Q+
TX_Q-
V
DDA
COMPRES1
TEST4
TEST3
TEST2
TEST1
TEST0
GNDd
MCLK
NC
ANT-SEL
ANT-SEL
RX-RF_AGC
V
DDD
GNDd
TX_IF_AGC
RX_IF_AGC
COMPCAP1
Simplified Block Diagram
ANT_SEL
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
THRESH.
DETECT
IF
DAC
I ADC
Q ADC
V
REF
I/O
TX_I±
I DAC
TX_Q±
Q DAC
TX_IF_AGC
TX_AGC_IN
44MHz MCLK
TX
DAC
TX
ADC
6
6
MOD
1
1
7
AGC
CTL
RX_I±
RX_Q±
6
6
DEMOD
DATA I/O
7
6
TX
ALC
HFA 3861 BBP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
PRISM and PRISM logo are trademarks of Intersil Corporation.
HFA3861
Table of Contents
PAGE
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Port (4 Wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX I/Q A/D Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX_AGC_IN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX I/Q DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spread Spectrum Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGC Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demodulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PN Correlators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Demodulation in the CCK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overall Eb/N0 Versus BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thin Plastic Quad Flatpack Packages (TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
3
4
5
6
7
7
8
8
8
9
9
9
9
10
12
12
12
13
13
14
14
15
16
17
17
19
19
19
19
20
20
21
23
33
33
35
2
Typical Application Diagram
1
1
7
WEP
ENGINE
RADIO
DATA
INTERFACE
CPU
AGC
CTL
HFA3841
MAC
RF
DAC
RF
ADC
IF
DAC
I ADC
Q ADC
REFOUT
PLL
IF
LO
I DAC
Q DAC
REF IN
7
6
HFA3861 BBP
EXTERNAL
MEMORY
TX
ALC
TX
DAC
TX
ADC
REF IN
HFA3783 QUAD IF
6
MOD
GP SERIAL
PORTS
MEMORY
ACCESS
ARBITER
6
I/O
I/O LO
RADIO
CONTROL
PORTS
6
DEMOD
6
RF
LO
HFA3963
RFPA
REF IN
HOSTPC
INTERFACE
3
16-BIT
PIPELINED
CONTROL
PROCESSOR
HFA3683 RF/IF
CONV
HOST
INTERFACE
LOGIC
PLL
HFA3861
44MHz MCLK
DIFFERENTIAL SIGNALS
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3861
For additional information on the PRISM® chip set, call (407) 724-7800 to access
Intersil’ AnswerFAX system. When prompted, key in the four-digit document
number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in the Typical Application Diagram, and
correspond to the appropriate circuit.
HFA3861
Pin Descriptions
NAME
V
DDA
(Analog)
V
DDD
(Digital)
GNDa
(Analog)
PIN
12, 17, 22,
31
2, 8, 37, 57
9, 15, 20,
25, 28,
TYPE I/O
Power
Power
Ground
Ground
I
I
I
I
O
DESCRIPTION
DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip).
DC power supply 2.7 - 3.6V
DC power supply 2.7 - 3.6V, ground (Not Hard wired Together On Chip).
DC power supply 2.7 - 3.6V, ground.
Voltage reference for A/D’s and D/A’s
Current reference for internal ADC and DAC devices. Requires a 12kΩ resistor to ground.
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for
differential drive of antenna switches.
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for
differential drive of antenna switches.
Analog input to the receive power A/D converter for AGC control.
Analog drive to the IF AGC control.
Drive to the RF AGC stage attenuator. CMOS digital.
Input to the transmit power A/D converter for transmit AGC control.
Analog drive to the transmit IF power control.
When active, the transmitter is configured to be operational, otherwise the transmitter is in standby
mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to
the HFA3861. The rising edge of TX_PE will start the internal transmit state machine and the falling
edge will initiate shut down of the state machine. TX_PE envelopes the transmit data except for the
last bit. The transmitter will continue to run for 4µs after TX_PE goes inactive to allow the PA to shut
down gracefully.
TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3861. The data is received serially with the LSB first. The data is clocked in the
HFA3861 at the rising edge of TXCLK.
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3861, synchronously. Transmit data on the TXD bus is clocked into the HFA3861 on the rising
edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock
will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3861 is ready to receive the data packet from the
network processor over the TXD serial bus.
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are
described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with
MD_RDY.
RXCLK is the bit clock output. This clock is used to transfer Header information and payload data
through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is
held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been
detected. Data should be sampled on the rising edge. This polarity is programmable and can be
inverted.
GNDd (Digital) 1, 7, 36, 43,
56
V
REF
I
REF
RXI
, +/-
RXQ
, +/-
ANTSEL
16
21
10/11
13/14
39
ANTSEL
40
O
RX_IF_DET
RX_IF_AGC
RX_RF_AGC
TX_AGC_IN
TX_IF_AGC
TX_PE
19
34
38
18
35
62
I
O
O
I
O
I
TXD
58
I
TXCLK
55
O
TX_RDY
59
O
CCA
60
O
RXD
53
O
RXCLK
52
O
4
HFA3861
Pin Descriptions
NAME
MD_RDY
PIN
54
(Continued)
TYPE I/O
O
DESCRIPTION
MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data
transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns
to its inactive state when RX_PE goes inactive or an error is detected in the header.
When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled.
SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal
registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the
register address immediately followed by 8 more bits representing the data that needs to be written
or read at that register. In the 4 wire interface mode, this pin is tristated unless the R/W pin is high.
SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire
interface described in this data sheet. It should not be left floating.
R/W is an input to the HFA3861 used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read
while a low level is a write.
CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
in the appropriate section of this data sheet.
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3861 goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up.
Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to
generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/ 24-
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-.
Compensation capacitor
Compensation capacitor
Compensation Resistor
Compensation Resistor
RX_PE
SD
61
3
I
I/O
SCLK
4
I
SDI
R/W
64
5
I
I
CS
6
I
TEST 7:0
51, 50, 49,
48, 47, 46,
45, 44
63
I/O
RESET
I
MCLK
TXI
+/-
TXQ
+/-
CompCap
CompCap2
CompRes1
CompRes2
42
23/24
29/30
33
26
32
27
I
O
O
I
I
I
I
NOTE: See CR10<3>.
External Interfaces
There are three primary digital interface ports for the
HFA3861 that are used for configuration and during normal
operation of the device as shown in Figure 1. These ports
are:
• The
Control Port,
which is used to configure, write
and/or read the status of the internal HFA3861
registers.
• The
TX Port,
which is used to accept the data that
needs to be transmitted from the network processor.
• The
RX Port,
which is used to output the received
demodulated data to the network processor.
In addition to these primary digital interfaces the device
includes a byte wide parallel
Test Port
which can be
configured to output various internal signals and/or data.
The device can also be set into various power consumption
modes by external control. The HFA3861 contains four
Analog to Digital (A/D) converters and four Digital to Analog
converters. The analog interfaces to the HFA3861 include,
the In phase (I) and quadrature (Q) data component inputs/
outputs, and the RF and IF receive automatic gain control
and transmit output power control.
5
Integrated technical exchanges
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