CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1.5MHz,
Unless Otherwise Specified
25
o
C
-
40
o
C TO 85
o
C
MAX
MIN
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
(End Point)
Differential Linearity Error, DNL
J
K
J
K
Gain Error, FSE
(Adjustable to Zero)
Offset Error, V
OS
(Adjustable to Zero)
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
J
K
J
K
J
K
Spurious Free Dynamic Range, SFDR
J
K
ANALOG INPUT
Input Current, Dynamic
J
K
J
K
TEST CONDITIONS
MIN
TYP
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±2.5
±2.0
±2.0
±2.0
±3.5
±2.5
±2.5
±1.5
12
-
-
-
-
-
-
-
-
-
±2.5
±2.0
±2.0
±2.0
±3.5
±2.5
±2.5
±1.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 1.5MHz, f
IN
= 1kHz
-
-
-
-
-
-
-
-
68.8
62.1
71.0
63.6
70.5
63.2
71.5
65.0
-73.9
-68.4
-80.3
69.7
75.4
69.2
80.9
70.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dB
dB
dB
dB
At V
IN
= V
REF
+, 0V
-
±125
±150
-
±150
µA
6-1779
HI5810
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1.5MHz,
Unless Otherwise Specified
(Continued)
25
o
C
PARAMETER
Input Current, Static
Input Bandwidth -3dB
Reference Input Current
Input Series Resistance, R
S
Input Capacitance, C
SAMPLE
Input Capacitance, C
HOLD
DIGITAL INPUTS
OEL, OEM, STRT
High-Level Input Voltage, V
IH
Low-Level Input Voltage, V
IL
Input Leakage Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Three-State Leakage, I
OZ
Output Capacitance, C
OUT
CLOCK
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Input Current
TIMING
Conversion Time (t
CONV
+ t
ACQ
)
(Includes Acquisition Time)
Clock Frequency
Internal Clock, (CLK = Open)
External CLK (Note 2)
Clock Pulse Width, t
LOW
, t
HIGH
Aperture Delay, t
D
APR
Clock to Data Ready Delay, t
D1
DRDY
Clock to Data Ready Delay, t
D2
DRDY
Start Removal Time, t
R
STRT
Start Setup Time, t
SU
STRT
Start Pulse Width, t
W
STRT
Start to Data Ready Delay, t
D3
DRDY
Clock Delay from Start, t
D
STRT
Output Enable Delay, t
EN
Output Disabled Delay, t
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
DD
+ I
AA
NOTE:
2. Parameter guaranteed by design or characterization, not production tested.
[i=s]This post was last edited by dontium on 2015-1-23 11:13[/i] 3-1:The simulation result is inconsistent with the result calculated in the book, the book says 2490nV[size=1]RMS[/size][size=2], the s...
I am using a 2440 board, and I want to expand the residentFlash in arm. I have repartitioned the Flash, and the DNW shows the following: 0: offset 0x0, size 0x30000 [boot] 1: offset 0x30000, size 0x30...
Analogue and Mixed Signal
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